United States

A comprehensive study of electric field (E-field) dependent endurance on Hf-based ferroelectric (FE) fatigue and breakdown mechanism is presented in this study. Under low E-field, reducing E-field worsens FE fatigue and constrains endurance but with no SILC increase as the result of the domain pinning. While under the high E-field stress, endurance is dominated by the field accelerated breakdown due to the increase of oxygen vacancy generation. By utilizing these distinct FE fatigue characteristics under different bias, the recoverable fatigue and prolonged cycle-to-breakdown is observed through a promising high frequency mixed-signal E-field operation.

IRPS 2022 Main Conference 

The Field-dependence Endurance Model and Its Mutual Effect in Hf-based Ferroelectrics

e-dependence

reliability fatigue

ferroelectrics

technical paper

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The current trend in the automotive industry towards increasingly detailed and more granular mission profiles (MPs) is also giving rise to an enormous number of various MPs, distinguishing each individual application and use case imaginable. To keep an overview in the face of this flood of data, to filter out and select the qualification relevant MPs, and to create a suitable and simply designed reliability requirement, a MP clustering approach using a quantile criterion is presented. This generic approach is universally applicable and therefore not limited to the automotive industry.
Based on equivalent test times (ETTs) and acceleration factors (AFs), after determining the quantile criterion, a representative MP can be selected either from an existing best fit MP or an artificially generated MP, obtained by numerical methods. Furthermore, the coverage of these MP requirements by technology reliability capabilities can be evaluated with ease. This approach is a generic concept and can therefore be applied to all well-known and commonly used damage accumulation and failure acceleration models. In the presented automotive case studies, the temperature accelerated Arrhenius model, multidimensional MPs with temperature and voltage acceleration, the temperature cycling Coffin-Manson model as well as a non-linear damage accumulation model are investigated.

Mission Profile Clustering Using a Universal Quantile Criterion

A physics-based system-level electromigration (EM) modelling platform is employed to simulate EM and its impact on the IR drop from the supply voltage to the standard-cells for a power delivery network design in a 3 nm logic node. The simulated PDN elicited high EM-tolerance. Despite EM voiding in multiple PDN segments, the EM induced IR-drop increase at the standard-cell level stayed below 3.3% without any catastrophic standard-cell failures. Use of ruthenium rails reduced IR-drop penalty of system EM by a factor of ~0.6 compared with copper rails. 

System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents

In the advanced technology process, owing to the low and tunable trigger voltage, diode-triggered SCRs (DTSCRs) are widely used in low-voltage applications with extremely narrow electrostatic discharge (ESD) design margins. The breakdown of DTSCRs ESD structure with abnormal leakage current under transmission line pulsing stressing was studied in this work. The physical origins of DTSCRs have been established through failure analysis (FA). The mismatch of the thermal expansion coefficient of local materials results in redundant stress. Such redundant stress induce the structure dislocations and cracks were captured by transmission electron microscopy at atomic scale. A multi-physical simulation is conducted to scrutinize the breakdown transient process.

Nanoscale Analysis of Breakdown Induced Crack Propagation in DTSCR Devices

Reliability qualification of HV interconnects is more complicated due to additional consideration of inter-metal impacts under the influence of HV operation. Unlike intra-metal structure, the film stack and bottom physical profile of inter-metal structure is uneven. This explains the reliability response showing dependence on metal line width and bias polarity. We show the E-field distribution is not uniform with the highest E-field density at the bottom corners of metal line. Hence, for a complete inter-metal TDDB reliability qualification, the impacts from test structure design, process variation, and testing methodology need to be considered.

Insights on Inter-metal Reliability Assessment of High Voltage Interconnects

In this work, Gigahertz (GHz) AC signals are stressed at the input terminal of 22 nm FDSOI inverters and the degradation behaviors of transistors in the inverter are found to be different from that under the single device stress. These transistors work under different bias schemes compared to the regular single device measurements, where the AC stress is applied at the gate and DC stress is applied at the drain. To more precisely characterize the transistor reliability in logic circuits, we design the layout to measure the actual degradation of transistors in the inverter directly. The noise margin of the inverter and SRAM cell comprised of this inverter is also studied. The results in this study show that, in a real inverter, the degradation of pMOSFET is overestimated if the BTI result of single device is used.

Degradation Behaviors of 22 nm FDSOI CMOS Inverter Under GHz AC Stress

Deep level effects and on-wafer reliability have been evaluated in 0.15 mm AlGaN/GaN HEMTs differing for buffer compensation (C or Fe) and for epitaxial structure (C-doped monolayer devices with only C-doped region; C-doped bilayer samples with a barrier between the channel and the C-doped region). In monolayer devices trapping effects lead to the presence of a long time constant (50s) in drain current transients, related to the presence of CN defects; interaction with deep levels in C-doped buffer leads to knee voltage walkout, Ron increase and recoverable IDS degradation. Negative trapped charge in the gate-drain region reduces the electric field with respect to bilayer devices. Results from semi-on and on-state step stress show that by using a ‘Bi-layer’ AlGaN barrier, the interaction between C-related deep levels and channel hot electrons can be effectively reduced, thus alleviating trapping effects and parametric degradation, and giving the opportunity of fully exploiting the improved confinement offered by the C-doped buffer, at the expenses of a tolerable decrease of breakdown voltage.


Deep level effects and degradation of 0.15 um RF AlGaN/GaN HEMTs with Mono-layer and Bi-layer AlGaN backbarrier

It is well-known that power devices used in high-energy physics and space applications are often subjected to high amounts of radiation. Therefore, it is essential to accurately predict the long-term degradation of these power devices in the presence of radiation. In this paper, we expose LDMOS transistors to various TID of gamma radiation, quantify the dose-dependent generation of interface traps and trapped charges using a novel charge pumping technique; and establish the universality of the degradation kinetics, and illustrate that the model and inferences drawn from the findings in this paper can be applied to other LDMOS devices as well.


Correlated Effects of Radiation and Hot Carrier Degradation on the Performance of LDMOS Transistors

Short-circuit capability with GaN HEMTs is demonstrated thanks to an integrated Short-Circuit Current Limiter (SCCL) and a commercial gate-driver with DESAT protection. The SCCL is applied to GaN HEMTs to achieve a sufficiently long short-circuit withstanding time (SCWT) while retaining competitive on-state resistance. The SCWT is tuned from 0.3 μs to 3 μs (a remarkable 10x increase) with a relatively small penalty in on-resistance, no leakage increase, no threshold voltage degradation and no reliability degradation. The gate driver has desaturation detection (DESAT) and soft shutdown circuitry to achieve a fast protection response of 800 ns with high noise immunity greater than 100 V/ns. The combination of GaN power devices with SCCL and a commercial gate driver with fastDESAT and high noise immunity allows short-circuit protection and fail-safe operation of GaN power electronics for additional robustness in motor drive applications.

Short-Circuit Capability with GaN HEMTs

  DRAM vendors today choose to keep the internal topologies of DRAM devices secret.  This decision introduces significant practical challenges for designers of memory controllers who wish to provide their own forms of Rowhammer defenses. This paper describes three such challenges and the vulnerabilities, inefficiencies, and overhead they introduce. Defenses implemented at the memory controller could reduce (if not eliminate) these deficiencies should internal DRAM topology be made available.

The Price of Secrecy: How Hiding Internal DRAM Topologies Hurts Rowhammer Defenses

The demand for high-performance computation continues to accelerate. To satisfy this increasing demand, modern server and high-performance computing systems are increasingly deploying nodes with greater heterogeneity and integration. Both trends reduce the cost of computation: heterogeneity by increasing absolute performance, and integration by reducing cost per computation. What has not changed, however, are the stringent reliability, availability, and serviceability (RAS) requirements for nodes used in server and high-performance computing systems. A high level of RAS is required to ensure that data centers deploying nodes can correctly perform computations over their expected lifetime.This paper describes the increased RAS challenges posed by increased heterogeneity and integration. The paper motivates these challenges using data gathered from production systems and presents a case study of the RAS implementation on a highly integrated, heterogeneous node: the AMD EPYC™ and AMD Instinct™ MI250X heterogeneous compute node. Finally, the paper provides a call for standardization to aid in meeting these goals for future data centers.

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Mission Profile Clustering Using a Universal Quantile Criterion

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Mission Profile Clustering Using a Universal Quantile Criterion

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

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