United States

A combined experimental/simulation analysis has been performed to study the gate reliability of GaN-HEMTs with p-type gate under pulse stress conditions. Results show that the time-dependent gate breakdown (TDGB) can be determined by two factors: i) the total ON-time during which the device is subjected to a positive gate bias before the failure; ii) the number of pulses, hence the number of switching phases from OFF- to ON-State and vice versa. The severity of the degradation ascribed to transition phases depends on the OFF-time (tOFF) and transition time (tTR = tRISE = tFALL). In particular, the shorter tOFFand tTR, the higher the Schottky junction voltage drop and the current peak during the switching phase, respectively. The higher voltage drop is ascribed to the semi-floating potential of the p-GaN layer. 

IRPS 2022 Main Conference 

Gate Reliability of p-GaN Power HEMTs Under Pulsed Stress Condition

tcad modeling.

pulsed gate stress

p-gan gate

hemts reliability

gallium nitride

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception) [![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing) [![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

Please log in to explore this event. You need to log in with the email address you registered with. Access credentials have been sent to your email. 

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Registration for this conference has now closed. We appreciate your interest and hope to welcome you at a future event. If you’d like to hear about similar upcoming events, please check our website or join our mailing list.

Registration for this conference has now closed.

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The self-protection of SOI RF switches is presented in this paper. TLP ESD test results show that the ESD protection performance of SOI RF switches is impacted by various parameters, including switch array gate channel length, finger width, finger number, and RF switch stack number. The physics of the SOI RF switch ESD protection mechanism is also studied by comparing TLP ESD test results from SOI RF switch splits and other ESD protection structures. It is concluded that the SOI RF switch self-protection process during ESD transients contains two mechanisms: NMOS channel conduction triggered by gate coupling effect and parasitic bipolar turning on. 

Characterization and Analysis of RF Switches in SOI Technology for ESD Protection

In this work an implicit finite element model of a Printed Circuit Board (PCB), connectors, and stiffener is developed. The effect of several parameters on the strain distribution on the board was analyzed. The PCB was bolted to an aluminum stiffener. The simulation went through several steps to consider the effect of the solder reflow process as well as bolt pretension forces and plug-in forces of the connectors. Based on the simulation, board warpage and bolt pretension forces had significant effect on board strain. 

Numerical Simulation and characterization of PCB Warpage

Voltage surges induced by electrostatic discharge (ESD) impacts on the backside of an integrated circuit (IC) chip in flip-chip packaging potentially causes reliability problems and even leads to malfunctioning. On-chip voltage waveform monitor circuits on its frontside evaluate the surge as high as 200 mV when ESD gun at 200 V is discharged to the Si substrate backside through the contact resistance of 5 kΩ to the backside of a 350 µm thick Si substrate. The distribution of voltages over the frontside area of an IC chip is measured and explained with full-system level backside ESD simulation. 


Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging

In this paper, a high holding voltage dual-directional silicon-controlled rectifier (SCR) with an embedded shunt path (HVDDSCR-ESP) for high-voltage I/O electrostatic discharge (ESD) protection is proposed. Based on the 0.13-μm BCD process, multi-current pulses that mimic the transmission line pulse (TLP) are applied to devices by using Sentaurus-TCAD. The results reveal that the proposed structure, compared with the conventional low-trigger dual directional SCR (LTDDSCR), has adjustable high holding voltage and good ESD robustness. In addition, the working mechanisms are also investigated, and the proposed device as the ESD cell is beneficial for the 12V applications and has no risk of latch-up.

A Novel Latch-Up-Immune DDSCR Used for 12 V Applications

Adhesion-Limit in Refractory Transition Metal (Mo) Contact Relay Operation at 300 °C— Avoiding Overestimation for Modern ICs

Adhesion-Limit in Refractory Transition Metal (Mo) Contact Relay Operation at 300 °C— Avoiding Implicated Overestimation for Modern ICs

Integrating CMOS circuits and qubits at cryogenic temperatures a key challenge to enable up-scaling of quantum computers. One approach to reduce power consumption is to optimize designs towards operation at lower supply voltages. However, this reduces the tolerable margins on variability and device to device variations. In this study, we present the time-zero variability and mismatch of nMOS transistors from room temperature down to 4K. We investigate the physical origins of variability at cryogenic temperatures. We estimate the influence of different on-current variability sources and observe that another source of mismatch, likely contact resistance, becomes dominant at low temperatures.

Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors

While LDMOS is one of the most widely used power transistors it has persistent reliability issues (e.g., HCD), because of the high applied bias.  Several efforts have been made to model HCD in TCAD. However, the lack of a feasible experimental approach to extract in LDMOS, made it challenging to verify the  obtained from TCAD. Here, we demonstrate the capability of the S2PCP technique to extract,  quantify the spatial and temporal evolution, identify the differences between experimental and TCAD and suggest possible physical mechanisms responsible. This analysis establishes robustness and identifies the limitations of TCAD modeling. 

A Critical Examination of the TCAD Modeling of Hot Carrier Degradation for LDMOS Transistors

Significant enhancement of hot-carrier degradation and time-dependent dielectric breakdown by mechanical stress was observed in CMOS FETs. Mechanical stress was induced locally in the channels of p- and n-type FETs by applying a vertical load with a diamond tip of a nanoindenter. The induced GPa level stress was calculated with finite element modeling. Mechanical stress induces a piezoresistance effect in both p- and n- channels, leading to an increase in source/drain leakage and drive currents and drastic enhancement of impact ionization. This in turn results in strongly enhanced hot-carrier degradation and hot-electron-induced punch-through effects in pFETs and enhanced hot-carrier degradation and time-dependent dielectric breakdown in nFETs. 

Observation of Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress

Hot electron trapping can significantly impact the performance of GaN-based HEMTs. Within this paper, the effect of current density and electric field on the severity of hot-electron degradation is presented. The experiments demonstrate that: (i) we can isolate the hot electron trapping processes, (ii) the hot-electron induced performance degradation follows a logarithmic kinetic, which can be modeled by rate equations, and (iii) the amount of current collapse has a linear dependence on the applied electric field and a logarithmic dependence on the current density, in agreement with theoretical equations.

Hot-Electron trapping in GaN-based HEMTs

Using a full quantum mechanical calculation, we investigate the fundamental validity of the Schottky emission model for its applications to electron injection in dielectrics from a metal or semiconductor electrode. We cover a wide range of electric fields from10kV/cm to 10MV/cm and temperatures for a large range of barrier heights. We conclude the Schottky emission model is only applicable for a very small class of dielectrics under 0.1MV/cm and at high temperatures over ~330°K.  For many defective dielectrics such as BEOL/MOL and MIMCAP dielectrics with a barrier height (FB ≥ 1eV), its conduction is negligible for electric fields larger than 0.1MV/cm while thermionic-field or field emission becomes dominant. If Schottky emission process is indeed valid, then the FN tunneling current must be smaller than that of the Schottky emission process with the same FB. Several misconceptions and malpractices as widely occurred in the dielectric community have been clarified. This work carries significant impact on BEOL Breakdown model development

Quantum Mechanical Connection of Schottky Emission Mechanism and Its implications on Breakdown Methodology and Conduction Modeling for BEOL Low-k Dielectrics

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Characterization and Analysis of RF Switches in SOI Technology for ESD Protection

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