United States

Integrating CMOS circuits and qubits at cryogenic temperatures a key challenge to enable up-scaling of quantum computers. One approach to reduce power consumption is to optimize designs towards operation at lower supply voltages. However, this reduces the tolerable margins on variability and device to device variations. In this study, we present the time-zero variability and mismatch of nMOS transistors from room temperature down to 4K. We investigate the physical origins of variability at cryogenic temperatures. We estimate the influence of different on-current variability sources and observe that another source of mismatch, likely contact resistance, becomes dominant at low temperatures.

IRPS 2022

Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors

cryogenic cmos

variability

quantum computing

technical paper

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Time-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.

A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies

The introduction of Ferroelectric Tunnel Junctions (FTJs) in embedded memory systems and in brain-inspired computing platforms requires a deeper understanding of their reliability and degradation mechanisms. Here we combine an extended stress/measure (DC I-V, PUND, C-f/G-f) set with a new FTJ small signal model, that specifically considers the physical properties and the role of each layer. Results reveal that reliability is ultimately limited by defect generation in the ferroelectric, in line with simulation on MFM devices. Asymmetry in the polarization-dependent leakage increase (due to defect generation) is found, that is associated with different stages (wake-up, fatigue, aging) of device lifetime.

Combining Experiments and a Novel Small Signal Model to Investigate the Degradation Mechanisms in Ferroelectric Tunnel Junctions

A novel Ferroelectric FET (FeFET) structure to enable multi-level cell (MLC) storage using a cleaved gate (CG) is proposed for the first time. The CG-FeFET’s gate is divided into two gates by an insulator. The CG-FeFET is optimized based on well-calibrated TCAD models. We perform an extensive design space exploration by evaluating: 1) the impact of the length of separation oxide (LOX) between source side gate (G_S) and drain side gate (G_D); 2) whether reading from G_S or G_D is better; 3) the best placement of the insulator between the two gates comparing symmetric (LG_S= LG_D) vs. asymmetric (LG_S≠LG_D) structure.  

Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage

A constant current stress scheme is implemented for endurance study on OTS-PCM devices for the first time. It provides a feasible method to estimate the read/write endurance for cross-point PCM products, which can save testing time for chips qualification.          

Endurance Evaluation on OTS-PCM Device using Constant Current Stress Scheme

Endurance ~ 1012 cycling of ferroelectric (FE) and antiferroelectric (AFE) HfZrO2 (HZO) capacitors are achieved experimentally by adjusting the programming pulse width (tp). The correlation between switching polarization (△P) and fatigue behavior of high endurance is discussed. For long tp (= 1 µs), AFE exhibits excellent endurance with &gt; 1010 cycles as compared with FE ~ 109 cycles. With shortening tP, the endurances of FE and AFE are significantly improved. There is no significant degradation until &gt; 1011 cycling is observed for FE with tp=20ns. 

Correlation between Access Polarization and High Endurance (~ 1012 cycling) of Ferroelectric and Anti-Ferroelectric HfZrO2

We propose an aging degradation suppression scheme at constant performance by controlling supply voltage and body bias for an FDSOI device. Reducing supply voltage while increasing body bias can maintain performance and suppress dynamic power and aging degradation caused by BTI. From measurement results of ring oscillators in a 65 nm    FDSOI, NBTI- and PBTI-induced degradations can be reduced by 29% and 10% at 1.5 V supply voltage and 0.15 V forward body bias paying the penalty of 2x leak power increase.

An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process

Hafnium oxide-based ferroelectric tunnel junctions (FTJs) are novel nonvolatile memory devices with promising advantages such as non-destructive readout in comparison with conventional ferroelectric random access memories. Reliability aspects of FTJ devices need to be investigated, including endurance, retention, ferroelectric switching, breakdown characteristics, and memory window. These characteristics exhibit promising results at room temperature; however, further analysis is required at different operating temperatures. In this work, we demonstrate the FTJ device characteristics at different temperatures varying from -40 °C to 60 °C.

Impact of Temperature on Reliability of MFIS HZO-based Ferroelectric Tunnel Junctions

To enable high-density cross-point arrays of magnetic memory a suitable access device is necessary. A promising candidate for this role is a metal-semiconductor-metal (MSM) tunneling device. In this work, the operation of an ultrathin Pt\6nm a-IGZO\Pt stack as an MSM selector is discussed. The focus is given to understanding the breakdown mechanism at high current regime, which prevents it from reaching the target current density. The breakdown is preceded by a gradual degradation process, which is manifested as an increase in high-field current after prolonged stress. This effect is recoverable – current returns to original value after sufficient delay time. Based on these observations, we propose a mechanism, where increased high-field current can be explained as a decrease in Schottky barrier height arising from stress-induced increase in oxygen vacancies.

Degradation mechanism of amorphous IGZO-based bipolar metal-semiconductor-metal selectors

In this work, we demonstrate experimentally an RRAM-based IMC logic concept with strong resilience to RRAM variability, even after one million endurance cycles. Our work relies on a generalization of in-memory Scouting Logic, and we demonstrate it experimentally with up to 16 parallel devices, a new milestone for RRAM in-memory logic. Moreover, we combine IMC with a new smart Multi-Level-Cell (MLC) programming algorithm resilient to conductance relaxation and demonstrate experimentally, for the first time, an IMC RRAM-based MLC 2-bit adder.

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory-Computing with up to 16 parallel operations

This paper investigates the
characterization of charge trapping and its modelling on hafnia-based
ferroelectric field effect transistors (FeFETs). Defect characterization on
MOSFETs can be done by studying threshold voltage shifts (DVth) as a function of charging and
relaxation times. At positive gate voltages one expects electron trapping in
the gate oxide to result in a positive shift of the threshold voltage (Vth). However, on a FeFET those conditions
will induce polarization changes in the gate oxide leading to a negative Vth-shift, complicating the characterization
of defect levels. We aim to alleviate these difficulties by modelling the
polarization and trapping in FeFETs over a wide range of timescales, suitable
for defect characterization. We demonstrate quantitative agreement on long
timescales with a static polarization model while a time-dependent polarization
model can be used for qualitative agreement over a wide range of times from 30
ms to 2 ks.

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Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors

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A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies

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