United States

Several designs of 1.2kV-rated 4H-SiC PiN diodes and Junction Barrier Schottky (JBS) diodes have been successfully fabricated with various P+ implantation conditions resulting in different junction profiles. P+ regions were implanted at both room temperature and elevated temperature in order to monitor the generation of Basal Plane Dislocations (BPDs) and study their impact on device long term reliability. It was found that, when the dose in the deeper portion of the junction (implemented by high energy) is well suppressed, static and long-term reliability performances of room temperature implanted devices can be maintained similar to those of high temperature implanted devices.

IRPS 2022

Static Performance and Reliability of 4H-SiC Diodes with P+ Regions Formed by Various Profiles and Temperatures

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Bias Temperature Instability refers to the widely known shift of the threshold voltage of metal-oxide-semiconductor field-effect transistors upon changes of gate bias and is typically measured at room temperature or above. The shift of the threshold voltage is caused by trapping/detrapping of charges in pre-existing defects located close to the semiconductor-insulator interface as well as the generation of new defects. Particularly silicon carbide transistors show a pronounced short-term trapping/detrapping behavior, which leads to threshold voltage variations already well below the microsecond time frame after gate bias changes. The physics of involved charge transfer reactions has been accurately described by non-radiative multiphonon transitions. We present evidence that in SiC devices radiative charge transitions are also present in a Bias Temperature Instability experiment, once the transistor is switched between accumulation and inversion or vice versa. Furthermore, we present a field-effect based pump-probe measurement that allows us to correlate the number of emitted photons after microsecond gate pulses to the threshold voltage recovery.

Optical Emission Correlated to Bias Temperature Instability in SiC MOSFETs

The leakage current and threshold voltage instability of NO nitrided SiC(1-100) m-face MOS devices was intensively studied. Nitridation at a typical temperature of 1250°C was found to reduce the onset field of Fowler-Nordheim tunneling current by about 1 MVcm-1. Moreover, systematic positive and negative voltage stress measurements revealed that the nitrided m-face MOS devices exhibit much larger threshold voltage shifts compared to a reference Si-face device. Despite the improvement in the MOS interface quality by NO nitridation, our results clearly indicate the drawbacks of nitridation for m-face MOS devices in terms of reliability.

Investigation of reliability of NO nitrided SiC(1-100) MOS devices

Threshold voltage instability in 4H-SiC MOSFETs was investigated by means of combined cyclic gate bias stress measurements and single gate bias point measurements. This allowed to separate the contributions of interface states (Nit) and near interface oxide traps (NIOTs) in the nitridated deposited gate oxides. Nanoscale chemical analyses by electron energy loss spectroscopy allowed to correlate these trapping states to the presence of a sub-stoichiometric silicon oxide (~1 nm) and carbon-related defects (&lt;1 nm) on different SiO2/4H-SiC interfaces In particular, the sub-stoichiometric silicon oxide was correlated to the interface states and the carbon-related defects have been correlated to the NIOTs.

SiO2/4H-SiC interfacial chemistry as origin of the threshold voltage instability in power MOSFETs

The circuit functionalities of Complementary Metal-Oxide-Semiconductor (CMOS) devices on 4H-SiC for digital and analog circuit applications beyond 200˚C have been extensively studied, however, the reliability of the devices on SiC needs to be demonstrated due to the traps at/near the dielectric interface. In this report, the reliability of n- and p- Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) has been studied on three different gate oxide conditions – thick thermally grown, ultrathin thermal + thick CVD oxide and ultrathin thermal + thin CVD oxide in terms of their bias temperature instability (BTI) measurement. The MOSFETs were stressed at various constant bias voltages at 150˚C and up to 105s. The threshold voltage shift due to positive bias on n-MOSFET is &lt;0.5V after 105s at +25Vwhile p-MOSFET shows a larger shift of -1.9V shift after 105s at -25V and 150˚C for ultrathin + thick CVD oxide. The report also establishes improvement in reliability of p-MOSFETs with ultrathin + CVD oxides over thermally grown oxides.

Bias Temperature Instability on SiC n- and p-Channel MOSFETs for High Temperature CMOS Applications

The suitability of a 12nm FinFET LDMOS offering toward a broad range of applications has been demonstrated with respect to key reliability aspects. The impact of well-known degradation mechanisms, such as conductive and non-conductive Hot Carrier Injection and the off-state Time Dependent Dielectric Breakdown is discussed. The impact of process and design optimization with respect to reliability and time zero performance is addressed as well.

Optimized LDMOS Offering for Power Management and RF Applications

The effect of reverse body bias on hot carrier (HCI) reliability is studied in details at CHE (channel hot carrier) and DAHC (drain avalanche hot carrier) stress conditions in advanced standard gate n-channel FinFET transistors.  HCI degradation is found to be independent of reverse body bias, when the body bias, Vb is low (0V ~ -1V).  However, HCI starts to aggravate at further negative Vb (-1V ~ -2V) for both CHE and DAHC conditions, showing strong dependence on the transverse electric field. The physical mechanism is attributed to the increased e-h pair generations, enhancing electron trapping in the gate oxide. This study addresses a key reliability constraint for circuit designers while designing tuned body bias circuitry

Reverse Body Bias Dependence of HCI Reliability in Advanced FinFET

In this work, analog and RTN performance of transistors operating in low current conditions were investigated. It is proven that in subthreshold regime the RTN signal is driven by defects located at the STI edges. Reducing the amount of electrical impurities situated at the device periphery lead to evident RTN improvement without significant change in targeting or reliability, and reduce the noise sensitivity to temperature and body bias. Empirical correlation between RTN and intrinsic gain was also reported, which can be used for fast inline process monitoring of defects located in the STI edges.

Impact of Electrical Defects located at Transistor Periphery on Analog and RTN Device Performance

In this paper, we present a detailed study of negative bias temperature instability (NBTI) and Time dependent dielectric breakdown (TDDB) reliability in p-type stacked gate- all -around (GAA) Nanosheet (NS) transistors with SiGe channel and compared with NS Si pFETs. Robust NBTI and TDDB reliability performance is achieved on SiGe gate-all-around NS.


SiGe Gate-All-around Nanosheet Reliability

The issues related to the failure analysis of 4H-SiC PowerMOSFET failed at EWS (Electrical Wafer Sorting) such as the channel leakage current is investigated. In particular, EWS is carried out in the namely defect free wafers areas monitored at several inline levels. This paper reports on the electrical based methods used to spot macroscopic defects even if they are invisible at optical wafer inspections. In particular, the current separation technique on source and gate terminals allowed to reduce the number of  candidate samples to be investigated

Failure analysis addressing method of optically undetected defectivity on 4H-SiC PowerMOSFET epitaxial layer

Resistive random-access memory (RRAM)-based in-memory computing (IMC) recently became a promising paradigm for efficient deep neural network acceleration. The multi-bit RRAM arrays provide dense storage and high throughput, whereas the physical non-ideality of the RRAM devices impairs the retention characteristics of the resistive cells, leading to accuracy degradation. On the algorithm side, various hardware-aware compression algorithms have been proposed to accelerate the computation of deep neural networks (DNNs) computation. However, most recent works individually consider the "model compression" and "hardware robustness". The impact of the RRAM non-ideality for the sparse model is still under-explored. In this work, we present a novel temperature-resilient RRAM-based IMC scheme for reliable DNN inference hardware. Based on the measurement from a 90nm RRAM prototype chip, we first explore the robustness of the sparse model under the different operating temperatures (25°Cto 85°C). On top of that, we propose a novel robustness-aware pruning algorithm, then further enhance the model robustness with a novel sparsity-aware noise-injected fine-tuning. The proposed scheme achieves &gt;92% CIFAR-10 inference accuracy after one-day operation, which is &gt;37% higher than the state-of-art method.

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Static Performance and Reliability of 4H-SiC Diodes with P+ Regions Formed by Various Profiles and Temperatures

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Optical Emission Correlated to Bias Temperature Instability in SiC MOSFETs

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