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In this work, analog and RTN performance of transistors operating in low current conditions were investigated. It is proven that in subthreshold regime the RTN signal is driven by defects located at the STI edges. Reducing the amount of electrical impurities situated at the device periphery lead to evident RTN improvement without significant change in targeting or reliability, and reduce the noise sensitivity to temperature and body bias. Empirical correlation between RTN and intrinsic gain was also reported, which can be used for fast inline process monitoring of defects located in the STI edges.

IRPS 2022 Main Conference 

Impact of Electrical Defects located at Transistor Periphery on Analog and RTN Device Performance

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#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

CV characteristics of MOS capacitors are classically measured in a few seconds using a capacimeter. Yet it limits the range of useful characterization that can be performed on these devices. For instance BTI reliability characterization is limited by the unavoidable recovery during every measurement step. Likewise, it is almost impossible to characterize properly the hysteresis effect present in some oxides.  Therefore we propose new ultra-fast and powerful CV techniques for MOScap, able to overcome the time limitations of former techniques.


Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors

Bias Temperature Instability refers to the widely known shift of the threshold voltage of metal-oxide-semiconductor field-effect transistors upon changes of gate bias and is typically measured at room temperature or above. The shift of the threshold voltage is caused by trapping/detrapping of charges in pre-existing defects located close to the semiconductor-insulator interface as well as the generation of new defects. Particularly silicon carbide transistors show a pronounced short-term trapping/detrapping behavior, which leads to threshold voltage variations already well below the microsecond time frame after gate bias changes. The physics of involved charge transfer reactions has been accurately described by non-radiative multiphonon transitions. We present evidence that in SiC devices radiative charge transitions are also present in a Bias Temperature Instability experiment, once the transistor is switched between accumulation and inversion or vice versa. Furthermore, we present a field-effect based pump-probe measurement that allows us to correlate the number of emitted photons after microsecond gate pulses to the threshold voltage recovery.

Optical Emission Correlated to Bias Temperature Instability in SiC MOSFETs

The leakage current and threshold voltage instability of NO nitrided SiC(1-100) m-face MOS devices was intensively studied. Nitridation at a typical temperature of 1250°C was found to reduce the onset field of Fowler-Nordheim tunneling current by about 1 MVcm-1. Moreover, systematic positive and negative voltage stress measurements revealed that the nitrided m-face MOS devices exhibit much larger threshold voltage shifts compared to a reference Si-face device. Despite the improvement in the MOS interface quality by NO nitridation, our results clearly indicate the drawbacks of nitridation for m-face MOS devices in terms of reliability.

Investigation of reliability of NO nitrided SiC(1-100) MOS devices

We show our attempt to design space-grade low-power CMOS LSIs enhanced by magnetic tunnel junctions (MTJs). The validity is discussed by using high-energy heavy-ion experiments and macrospin simulations combined with single-event transient noise current modeling. Possible latent damage induced by heavy ions are also explored.

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability

Time and drain bias dependence of HCD under peak ISUB (VG ~ VD/2) stress are modeled. Published n-MOSFET data for different LCH (2.0µm to 37nm), TOX (35nm to 1.85nm), type of junction (HDD, LDD/HDD, SDE/HDD) and stress VD (8V to 1.6V) are analyzed. A compact model is used to model the time kinetics and to explain its difference (i.e., power law or non-power law) in devices having different types of junctions. The dominant energy model is used for VD dependence, and the model parameters are obtained with scaling. The time kinetics and VD dependence are also modeled using TCAD simulations.

Modeling Time and Bias Dependence of Classical HCD Mechanism (Peak ISUB Stress) in n-MOSFETs

Ultrafast measurements (with 10μs delay) are done to characterize the Negative Bias Temperature Instability (NBTI) and Hot Carrier Degradation (HCD) induced threshold voltage shift (ΔVT) in p-channel Gate All Around Stacked Nano-Sheet (GAA-SNS) Field Effect Transistors (FETs). A model framework is proposed to estimate the measured ΔVT time kinetics during and after NBTI and HCD stress. The BTI Analysis Tool (BAT) framework is calibrated using pure NBTI data (drain bias, VD, at 0V) across gate bias (VG) and temperature (T) and is subsequently used to estimate the underlying NBTI contribution during and after HCD stress under full VG/VD space in the presence of Self-Heating (SH) effect. The pure HCD kinetics is calculated using an empirical model, with VG, VD and T dependence incorporated via a vertical field enhanced dominant energy model.

Decoupling of NBTI and Pure HCD Contributions in p-GAA SNS FETs Under Mixed VG/VD Stress

The suitability of a 12nm FinFET LDMOS offering toward a broad range of applications has been demonstrated with respect to key reliability aspects. The impact of well-known degradation mechanisms, such as conductive and non-conductive Hot Carrier Injection and the off-state Time Dependent Dielectric Breakdown is discussed. The impact of process and design optimization with respect to reliability and time zero performance is addressed as well.

Optimized LDMOS Offering for Power Management and RF Applications

The effect of reverse body bias on hot carrier (HCI) reliability is studied in details at CHE (channel hot carrier) and DAHC (drain avalanche hot carrier) stress conditions in advanced standard gate n-channel FinFET transistors.  HCI degradation is found to be independent of reverse body bias, when the body bias, Vb is low (0V ~ -1V).  However, HCI starts to aggravate at further negative Vb (-1V ~ -2V) for both CHE and DAHC conditions, showing strong dependence on the transverse electric field. The physical mechanism is attributed to the increased e-h pair generations, enhancing electron trapping in the gate oxide. This study addresses a key reliability constraint for circuit designers while designing tuned body bias circuitry

Reverse Body Bias Dependence of HCI Reliability in Advanced FinFET

In this study, we report an ultra-fast C-V (&gt;4 GHz) measurement methodology for characterizing the high-frequency polarization phenomena in high-k dielectric films. Both HfO2
and Al2O3 films show a significant permittivity decrease under GHz frequencies due to the suppression of ionic polarization. It is the first direct observation of separating ionic and electronic polarization in ultra-thin high-k dielectric films, so far. The phenomena found in this study could be very important for understanding relative physical mechanisms in advanced electron devices, such as ferroelectric and analog devices using high-k dielectric films.

GHz C-V Characterization Methodology and Its Application for Understanding Polarization Behaviors in High-k Dielectric Films

Assessment of transistor degradation in analog circuits during aging effect is challenging due to wide spread of operating points. This paper presents our proposed characterization approaches of full ID-VG
degradation for large and nanoscale devices respectively. Threshold voltage shift and mobility degradation in large devices can be extracted simultaneously with fast measurement speed (tm=3us). Based on this, full ID-VG
degradation can be assessed intuitively. Impacts of individual defects on full ID-VG degradation in nanoscale devices are characterized with the proposed approach with high resolution. Thus this paper provides a helpful solution to the characterization of device degradation in analog circuits.

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Impact of Electrical Defects located at Transistor Periphery on Analog and RTN Device Performance

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Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors

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