United States

We present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate. This model is based on the precise estimation of voltage across MTJ at bit-cell level derived from compact model and design simulations to cover the product level endurance performance from MTJ diameter, resistance-area product, and temperature effects. We discuss the implications of pre/post MTJ switching, circuit variations and write pulse on MRAM endurance. By using design-process-test co-optimization, we show robust MRAM product reliability to meet &amp;gt;1M cycles with solder reflows and path towards achieving &amp;gt;E12 cycles for cache applications.

IRPS 2022

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability with Reduced Circuit and Process Variabilities

tddb

cache memory

stt-mram

We present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate. This model is based on the precise estimation of voltage across MTJ at bit-cell level derived from compact model and design simulations to cover the product level endurance performance from MTJ diameter, resistance-area product, and temperature effects. We discuss the implications of pre/post MTJ switching, circuit variations and write pulse on MRAM endurance. By using design-process-test co-optimization, we show robust MRAM product reliability to meet &gt;1M cycles with solder reflows and path towards achieving &gt;E12 cycles for cache applications.

technical paper

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

We investigate and model the threshold voltage instabilities of 4H-SiC power MOSFETs at room and cryogenic temperatures, based on wide time range (from µs to ks) PBTI analysis. We show that for T &gt; 200 K a stretched (log-like) de-trapping transient dominates the recovery kinetics, while at lower temperatures (down to 80 K) a fast exponential component is also visible. The charge de-trapping process is modeled as a distribution of traps spread over the midgap, that causes the threshold instability. Results indicate: i) one narrow gaussian energy distribution at the interface, visible at low temperature, which explains the exponential transient behavior for T &lt; 200 K; ii) a broader distribution deeper in energy, that is considered to take into account the logarithmic de-trapping kinetics at higher temperatures and the threshold static shift with temperature. The proposed modeling framework can accurately reproduce the experimental results.

Analysis and Modeling of Vth Shift in 4H-SiC MOSFETs  at Room and Cryogenic-Temperature

We investigate the mechanism governing threshold voltage (VTH) hysteresis in packaged SiC MOSFETs. A double-ramp measurement method was employed for this scope, being able to accurately evaluate the time-dependent recovery of the positive VTH shift induced by the sweep-up of the gate voltage. Particularly, we studied the effect of the (i) gate driving voltage (VGH), (ii) recovery time (TOFF) and (iii) temperature (T) on the VTH hysteresis. No appreciable differences were observed among data collected at different VGH, whereas a recovery speed-up was observed at higher T values. Temperature dependent measurement of VTH recovery yielded a 0.3 eV activation energy, that has been associated to SiC/SiO2 interface traps located ~0.3 eV below the SiC conduction band.

Identification of Interface States responsible for VTH Hysteresis in packaged SiC MOSFETs

At the 7-nm bulk FinFET node, latchup effects are seen as limited current increases. In this work, 7-nm node latchup susceptibility is evaluated for terrestrial and space environments as a function of supply voltage, temperature, and particle LET. Holding voltage for latchups is strongly dependent on temperature and was observed to be within 100 mV of nominal supply voltage, therefore latchup can be sustained at elevated supply voltages. Latchup SE cross-section increases with increasing particle LET, increasing supply voltage, and increasing temperature. 

Latchup Vulnerability at the 7-nm FinFET Node

This work presents a high-voltage-tolerant (HVT) supply clamp for ESD protection, in which the current drive of the clamp during an ESD event is maximized without compromising reliability during normal operation. Similar to prior HVT clamps, ESD current shunting is provided by 3 cascoded NFETs; however, the trigger circuit is improved. The design is implemented in a 45-nm SOI CMOS technology and the clamp devices are sized for a 2-kV HBM protection level. As evidenced by TLP and VFTLP measurements, the new clamp offers 50% reduction of on-resistance and 0.6 V lower turn-on voltage, relative to the prior art.

A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology

Forksheet (FS) FETs are a novel transistor architecture consisting of vertically stacked nFET and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p- to nFET separation (p-to-n separation), thus enabling further logic cell area scaling without requiring gate length scaling. We report hot-carrier degradation (HCD) simulations of FS FETs and compare this architecture to nanowire (NW) and nanosheet (NS) FETs. HCD is shown to decrease with increasing sheet width in both NS and FS FETs when taking interface state generation into account. Considering that a FS FET can be made wider than an NS FET because of the reduced p-to-n separation, lower HCD for the FS FET is observed. Finally, we make an initial assessment of the impact of oxide defect charging in the FS wall. We confirm decreasing influence of fixed wall charge for increasing sheet widths and estimate that the overall impact of wall charging will stay under control at operating conditions.

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

We extend our framework for hot-carrier degradation (HCD) modeling by covering the impact of self-heating (SH), which has three main aspects: (i) perturbation of carrier transport, (ii) acceleration of the thermal contribution to bond breakage, and (iii) and shortening vibrational lifetime of the bond, i.e. reducing the multiple-carrier mechanism rate. We validate the framework against HCD data acquired in nFinFETs and pNWFETs under various stress conditions, analyze the importance of each of the aforementioned aspects, and explain why in n-channel FETs SH slightly inhibits HCD, while in p-channel devices HCD is accelerated by SH.

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-channel Transistors

A recent progress of NanoBridge (NB) technology is reviewed for embedded nonvolatile field-programmable gate array (FPGA) and memory (NVM) applications. The NB is a kind type of electrochemical resistive-change device using Cu ion migration from Cu interconnects into electrolyte. The NBs are integrated in a standard Cu-BEOL with keeping a PDK and an appropriate ON-conductance is tuned by programming currents depending on the applications. For a routing switch in the FPGA, two NBs are connected in series and each conductance is tuned to ~1mS to transfer signals and realize 78% area reduction compared with a conventional SRAM-FPGA. For the NVM application, that is tuned to ~0.2mS, which has 150oC over 10years retention with 30% change of the conductance, which is potentially applicable for automobile applications.  

NanoBridge Technology: Nonvolatile FPGA and Memory Applications

In advanced DRAM technology, buried-channel-array transistor (BCAT) will generate additional leakage during long-term read/write operations, leading to retention time reduction. In this work, we designed the accelerated aging test in wafer level and proposed a model for the long-term retention time prediction. By adding into conventional retention time simulation flow, the data of retention time at different operation time can be predicted. It was found that the aging can degrade retention time tail around 13% in 10 years. This work is thus helpful to the refresh scheme development considering aging effect.

New Insight into the Aging Induced Retention Time Degradation of Advanced DRAM Technologies

With the growth of high performance computing on many industrial sectors that includes mobile/network and data centers/servers, the need for continued technology scaling and advancements on new process technology have paved ways to manufacture advanced semiconductor products. High-k + Metal gate devices and most recently EUV lithography process have become a key enabler for the 7nm technology nodes and beyond [1]. These technologies are being adopted in the advanced DRAM nodes. DRAM memory uses various devices such as MOSFETs (w/ and w/o HK+MG), cell transistor, cell capacitor, and its reliability has also been considered according to the designed purposes. This paper reviews comprehensive reliability on all types of devices used at each circuit in 15nm DRAM memory. The intrinsic reliability of devices in peripheral regions was guaranteed with systematic wafer-level-reliability evaluation up to product level testing for 1000hrs. The reliability of transistors in core regions was verified using design for reliability, various test structures, and up to an accelerated product level aging test. With the suggested degradation modeling of the capacitor in cell regions, the result on 32GB DIMM field tested for over 1 years shows the best in class reliability results and meets 10yrs of lifetime.

Impact of Transistor Reliability on Memories and Memory Periphery Circuitry

This paper presents a new compact model for ESD diodes named Advance SPICE Model for ESD diodes (ASM-ESD). In addition to the current-voltage (I-V) and the capacitance-voltage (C-V) behaviors of the diode under normal operating conditions, ASM-ESD has capabilities to model a plethora of important effects critical for the ESD applications. Model features include the ability to capture the overshoot effects, ambient temperature effects, self-heating effect, post reverse breakdown resistance, parasitic BJT gain, transient behavior of BJT gain and reverse recovery effects in ESD diodes. ASM-ESD model formulations have a physical basis leading to an intuitive extraction flow. Model comparisons with measurements for DC I-V, C-V, and TLP with pulse widths ranging from 200 ns to 1.2 ns are presented. These results demonstrate model accuracy for a full range of ESD event scenarios. 

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Extended MTJ TDDB Model, and Improved STT-MRAM Reliability with Reduced Circuit and Process Variabilities

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Analysis and Modeling of Vth Shift in 4H-SiC MOSFETs at Room and Cryogenic-Temperature

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