United States

This presentation reports the experimental results of the fabricated 4H-SiC Lateral Junction Field Effect Transistor (LJFET) and cell-to-cell integrated Lateral Bi-directional JFET (LBiDJFET). It was found that the reverse conduction characteristics of SiC LJFET were better than the forward conduction characteristics in terms of on-state resistance. The conduction mechanism of LBiDJFET can be described by the series connection of the forward and reverse conduction of LJFETs. This intriguing behavior of the cell-to-cell integration approach is promising because it can greatly reduce the wafer area consumed while achieving the bi-directional functions.

IEEE WiPDA 2021

Demonstration of Cell-to-Cell Integrated 4H-SiC Lateral Bi-Directional Junction Field Effect Transistor (LBiDJFET)

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

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The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

poster

For efficient converter design, modeling of switching components must be both accurate and fast. A variety of simulation models
for SiC Power MOSFETs has been developed. To achieve adequate accuracy, models are adjusted to experimental data by applying fitting methods. However, proposed universal fitting methods result in high-dimensional optimization problems. Their computational inefficiency leads to either long run times or low accuracy. This paper proposes a new universal parameter fitting method that is at least twice as fast and yields a more accurate outcome than presented methods under comparable conditions. It effectively reduces the dimensionality of the parameter fitting optimization problem by sensitivity-based reduction of optimization parameters.
Thereby, it optimizes both model adjustment speed and accuracy, which are critical factors for an efficient converter design process. The method does not compromise flexibility as it is universally applicable to any SPICE model and can meet any model architecture preference.

Smart Universal Parameter Fitting Method for Modeling Static SiC Power MOSFET Behavior

This paper presents a method that extracts junction temperature of SiC MOSFETs by measuring a unique turn-on delay. In preceding work, the turn-on delay was identified as a particularly promising temperature-sensitive electrical parameter for SiC MOSFETs. The reasons for this are its simple calibration, its insensitivity to the device current, its linear temperature dependency as well as the particular behavior of the charge carrier mobility of SiC. However, state-of-the-art extraction circuits for turn-on delay only work with a limited time resolution. Thus, they can only be applied to slowly switched SiC MOSFETs. This work proposes a circuit for turn-on delay extraction with a time-to-digital converter that allows the time resolution to be significantly increased. Thereby, the circuitry allows utilizing turn-on delay as an effective temperature-sensitive electrical parameter for junction temperature extraction of SiC MOSFET operated with fast switching transients. The feasibility of the approach is experimentally validated in this work with a developed extraction circuit using a SiC MOSFET power module as a device under test.

Online Junction-Temperature Extraction Method for SiC MOSFETs Utilizing Turn-on Delay

In this paper, a comprehensive comparative analysis is performed on the short circuit (SC) withstand time and failure modes between a 650 V SiC Planar MOSFET, a 650 V SiC Trench MOSFET and a 650 V SiC Cascode JFET. The short circuit tests have been performed at a DC link voltage of 400 V with gate turn-OFF voltages at 0 V and -5 V. The results show that the SiC Cascode JFET failed in a source-to-drain short circuit with the gate still capable of blocking voltage while the SiC Planar and Trench MOSFETs failed with the Gate-Source (VGS) terminal short circuited and Drain-Source (VDS) terminals still capable of blocking voltage. Furthermore, short circuit withstand times measured on the SiC Planar and Trench MOSFETs showed an increase (20% for the Planar MOSFET and 9% for the Trench MOSFET) when the device gate voltages were turned-OFF with -5V compared to 0V. This was due to the increased inductance of the negative voltage gate driver reducing the peak short circuit current. In the case of the SiC Cascode JFET, there was no dependence of the short-circuit withstand time on the VGS turn-OFF voltage.

Comparison of Short Circuit Failure Modes in SiC Planar MOSFETs, SiC Trench MOSFETs and SiC Cascode JFETs

A low conduction resistance 1200 V/ 4 mΩ SiC power module is fabricated and characterized for its thermal performance. The design and fabrication of the power module is presented. The parasitic resistance distribution from the module prototype is measured and shows that it is critical to minimize the source bond wire and contact resistance for such low on-state resistance module. The steady-state thermal tests are performed, and the temperature distribution of the fabricated module is measured and validated. A FEA model of the SiC module is built and validated by the steady-state thermal tests. Then the transient thermal performance or surge current capacity is studied. It shows that at least 4 bond wires are required for each SiC die such that the module package will not limit the surge current capacity of SiC chips.

Development and Thermal Characterization of a Low Resistance SiC Module

A double-side cooled 10 kV, 25 A SiC MOSFET package is proposed which utilizes a wirebond-less molybdenum interconnect to alleviate thermomechanical stress and improve reliability. An effective junction-to-case thermal resistance of 0.17 ºC/W is achieved, enabling the package to dissipate a heat flux at the MOSFET surface in excess of 200 W/cm^2 with less than 30ºC temperature rise from the device junction to the package exterior. Thermal and thermomechanical finite element simulations were carried out to select materials and manufacturing processes that ensure manageable thermomechanical stress levels are maintained during fabrication and operation. Simulations were verified with experimental results and the package successfully demonstrated 150ºC continuous operation without degradation.

Thermal and Thermomechanical Analysis of a 10 kV SiC MOSFET Package with Double-Sided Cooling

GaNFast™ power ICs, use next-generation gallium nitride (GaN) to replace legacy silicon chips to enable up to 3x faster charging and 3x more power in half the size and weight for mobile fast chargers, consumer electronics, solar, data centers and EVs, replacing silicon in a market worth over $13B by 2026. Now, a next-generation enables even higher efficiency, autonomy and reliability with precision sensing of system current, voltage and temperature and real-time control and protection. External monitoring components – such as large, lossy sense resistors – are eliminated, reducing system power loss, reducing complexity and reducing cost. This new GaNFast generation is a core element as we “Electrify Our World™” and accelerate the conversion away from fossil fuel sources and loads. As well as enabling efficiency improvements that reduce the carbon emissions of target applications, small die-size, fewer manufacturing process steps and integrated functionality mean that GaNFast power ICs have up to 10x lower CO2 footprint than silicon-based solutions, and save 4 kg CO2 per IC shipped, vs. equivalent legacy silicon chips.

Advances in GaN Power ICs: Efficiency, Reliability & Autonomy

SiC semiconductor technology has enjoyed rapid market adoption in the last few years. SiC MOSFETs have been adopted in a variety of markets such as solar inverters, industrial power supplies, and EV onboard and off-board chargers. But the rapid adoption of SiC for the drive train inverters in Battery Electric Vehicles is changing the market landscape for SiC. It is being adopted in these inverters because it offers a 5-10% improvement in efficiency, which results in either extended range for the vehicle for a given battery charge, or a reduction in the battery pack required to go a certain distance. A large number of automotive OEMs now have SiC targeted for incorporation into their EV drives. SiC power device manufacturing is based now on 150 mm substrates, allowing cost reduction over recent years. As the market grows further, the push to 200 mm substrates is inevitable, and Cree | Wolfspeed’s new wafer fab will be the first to start production on 200 mm.

SiC MOSFETs and the Drive for Electric Vehicles

With unrivalled better technology-specific figure-of-merits SiC MOSFETs and GaN HEMTs have started to conquer high power applications such as Mobile phone chargers, On-board chargers and Motor drives replacing IGBTs or Superjunction devices. Driven by ever higher demands on power density and efficiency and new trends such as bidirectional power flow for vehicle-to-x applications, wide bandgap power devices have turned into a focal point of design activities. In all of these applications a simple replacement of IGBTs or Superjunction devices by wide bandgap devices may bring already some benefits. The full potential of wide bandgap devices, however, will only be reached when being combined with perfectly matching topologies and control. In motor drives e.g. replacing the IGBTs of a B6 bridge with SiC MOSFETs may result in better efficiency in light load and urban drive cycles. However, switching speed limitations down to around 5V/ns to avoid e.g. partial discharge in the insulation of the motor windings or reflections in long cables, will prevent to increase switching frequencies substantially. In contrast, changing the topology from a voltage source inverter to a current source inverter, which creates a continuous voltage on the machine, opens up a completely new optimization range both for the electric machine and its inverter. Similarly, a transition from modular single phase power stages into true 3-phase active frontends using synergetic control options enables much higher power density for on-board chargers. The presentation will start with a few key characteristics of the involved technologies and their perspective and will highlight system advantages of wide bandgap power devices in a few selected key applications such as Onboard chargers and Motor drive.

On the benefits of SiC and GaN in high power applications

Integrated circuits made using GaN-on-Si substrates have been in production for over seven years. During that time, GaN-based ICs have evolved from pure discrete devices to monolithic half-bridge devices and then onto power FETs that included their own monolithically integrated driver, and more recently, to fully monolithic power stages including power FETs, drivers, level shifting circuits, logic, and protection. In this talk we will look at the roadmap of GaN-on-Si integration and show how the role of discrete transistors is destined to diminish to near-zero in the next few years.

Gallium Nitride Integration and the End of Discretes

GaN power HEMTs are known to offer high switching speed, low on-resistance and much better FOM when compared to their silicon counterparts. However, the ability to operate with high power density in a smaller form factor presents new challenges for reliable and robust operation. Traditional gate driver designs for silicon-based power devices are catered to lower frequencies with large tolerance on the gate voltage swing. They do not adequately address some of the reliability issues that are unique to GaN power transistors. This talk will provide a quick review on the gate driving requirements and limitations for GaN power HEMTs. This is followed by a survey of novel smart gate driving techniques that can further exploit the performance and enhance the reliability of GaN power devices. Topics to be covered include intelligent gate driving schemes such as active gate driving, dead time optimization, and current balancing. Emphasis will be given to designs that can be integrated and those that can monitor the devices for optimum performance and safe operation. Protection features such as short-circuit detection, gate overvoltage prevention, temperature monitoring and compensation will also be discussed. Monolithic integration of power GaN ICs is an exciting area of development with increasingly sophisticated designs reported in recent years. Fully integrated GaN building blocks and state of the art designs will be addressed.

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Smart Universal Parameter Fitting Method for Modeling Static SiC Power MOSFET Behavior

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Advances in GaN Power ICs: Efficiency, Reliability & Autonomy

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