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The target of manufacturing the GaN-on-Si HEMT with advanced CMOS process lines has been continuously pursued. This work reports on a low contact-resistance. Au-free ohmic contacts of an undoped AlGaN/GaN HEMTs on
silicon. These results are believed to promote the development of the GaN-on-Si HEMT compatible with the CMOS process line.

2021 IEEE WiPDA 

Low Contact Resistance CMOS-Compatible RF GaN-on-Silicon HEMTs

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

### Please select the button below to view and download the session papers. The Virtual Proceedings PDF can be downloaded [here.](https://drive.google.com/file/d/171y2_u63V-pc9-bC-eZgHLzJou2oCfST/view?usp=sharing)

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This event requires a registration to attend, please register [here](https://web.cvent.com/event/536cea3d-4c0d-4d50-8939-529979d80785/summary) to purchase a ticket. 

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

technical paper

During power cycling tests, a precise junction temperature estimation is necessary for a correct interpretation of the test results and it is even more important, when the test results are used for lifetime modeling. For SiC MOSFETs, a common approach is to use the VSD-Method, which was reported to deliver accurate junction temperature readings. However, given the variety of device designs and technologies available on the market, this cannot be taken for granted for all SiC MOSFETs. For that purpose, different aspects of the accuracy of the VSD-Method were investigated in this work, by comparing the junction temperature reading obtained by the VSD-Method, with the actual chip temperature, measured by thermography for two different SiC MOSFET designs. Whereas one design lead to accurate temperature readings, the other exhibited a significant deviation between the temperature measured by thermography and the temperature reading by the VSD-Method. Furthermore, the impact of the gate voltage on the temperature reading of the VSD-Method was investigated. Both designs exhibit a consistent temperature reading for gate voltages 2V above and below the maximum rated negative gate voltage for a wide range of sensing currents. Hence, the results show, that a systematic measurement error can occur for some SiC MOSFET designs, which may cause a misinterpretation of power cycling test results. Therefore, it is important to verify the accuracy of the temperature estimation when deploying the VSD-Method for SiC MOSFETs, particularly when comparative tests are performed or the test results are used for lifetime modeling.

Investigation on the Accuracy of the VSD-Method for Different SiC MOSFET Designs Considering Different Measurement Parameters

This paper reports about 10kW-class 650V-rated GaN switches. GaN-on-Si HEMTs with maximum current of 780A and 33.2mm2 die area were fabricated by chip scaling and intrinsic device shrink which gave improved RON*A area figure of merit. Tight integration with a low-voltage Si MOSFET results in a cascode switch with a high threshold of 4V, stable dynamic on-resistance of 14 milliohms for up to 750V VDS and single-chip-like simplicity in TO-247 packages. Using a simple gate drive of 0-12V and drive current below 0.7A, the GaN FET exhibits faster switching and 2x lower switching losses than a competing SiC MOSFET. When tested in a 240V:400V half-bridge synchronous boost converter, it was possible to get 12kW output power with >99% peak efficiency at 3kW.

650V/780A GaN Power HEMT Enabling 10kW-Class High-efficiency Power Conversion


This paper presents the evaluation of a 650-V, 100- A, 22-mΩ rated D3GaN (Direct Drive Depletion-mode) power switch (V22TC65S1A) from VisIC Technologies, which is designed for electric vehicles (EV) powertrain inverter applications. The static and dynamic performance as well as the surge-energy and short-circuit robustness of the D3GaN were evaluated in a top- cooled surface-mount device package. Multiple customized test boards were employed to evaluate the switching loss, dynamic on- resistance, gate charge (Qg), and robustness. The D3GaN switch has shown a small total Qg, high breakdown voltage, positive threshold voltage, small switching-energy loss, fast switching speed, and good robustness. These advantages make the D3GaN switch an attractive candidate for high-power EV powertrain inverter applications. To the best of our knowledge, this paper presents the first comprehensive evaluation of a high-power GaN device targeted for EV inverter applications.

Evaluation of 650V, 100A Direct-Drive GaN Power Switch for Electric Vehicle Powertrain Applications

We present a reduced physics-based thermal model to predict the thermal performance of Chip Scale Package (CSP) GaN FETs mounted to printed circuit boards (PCBs) and provide an easy-to-use thermal characterization tool for engineers and designers to quickly assess thermal management strategies. The heat conductance from the GaN FET to both the PCB side and to the “case” (i.e., die exposed surface) are modeled using resistive-network circuit modeling. The thermal resistance in each conductance path is presented for different parameters relating to PCB construction (stack-up, area, via density), FET size, and cooling approach (TIM material, heat spreader and heatsink). A comprehensive set of thermal finite-element simulations was run over the set of parameters. The results, presented in easy “look-up” style graphs, show that even with a small footprint, GaN FETs power-handling capability can be extended when effectively cooled using a simple PCB design and thermal management approach.

Quick Thermal Performance Estimation of Chip Scale Packaged GaN FETs using a Simple Circuit Model

This work reports an on-wafer study of avalanche behavior and failure analysis of in-house fabricated 1.3 kV GaN-on-GaN P-N diodes. DC breakdown is measured at different temperatures to confirm avalanche behavior. Diode’s avalanche
ruggedness is measured directly on-wafer using a modified unclamped inductive switching (UIS) test set-up with an integrated thermal chuck and high-speed CCD for real-time imaging during the test. The avalanche ruggedness of the GaN P-N diode is evaluated and compared with a commercial SiC Schottky diode of similar voltage and current rating. Failure analysis is done using SEM and optical microscopy to gain insight into the diode’s failure mechanism during avalanche operation.

On-Wafer Investigation of Avalanche Robustness in 1.3 kV GaN-on-GaN P-N Diode Under Unclamped Inductive Switching Stress

GaN transistors, and more recently integrated circuits, have been in mass production for over a decade [1] with several manufacturers reporting tens of millions of units shipped with billions of hours in actual end-use applications. The track record has been extraordinarily successful, and one of the key reasons is that GaN devices are far more rugged than their silicon MOSFET ancestors [2].
Recently, Efficient Power Conversion (EPC) did a series of tests to take eGaN FETs beyond their datasheet limits to quantify the effects of large amounts of overstress voltage and current. This paper will examine the results and those tests to show how operation under extreme conditions for long periods of time can be a practical new tool for power system design engineers.

Extreme GaN – What Happens When eGaN® FETs Are Exposed to Voltage Levels Well Above Data Sheet Limits

This paper studies switching behavior and dynamic on-state characteristics of lateral 10 mm depletion-mode β-Ga2O3 met-al-oxide-semiconductor field-effect transistors (MOSFETs). Improvements in device technology and fabrication enable hard-switching operation with an increase of the maximum blocking voltage to 400 V at 0.26 A load current in a double-pulse test configuration. Compared to static measurements, dispersion effects lead to an increased on-resistance in hard-switched operation, which becomes especially pronounced at blocking voltages above 200 V. The extend of dynamic Ron-increase further depends on several operation conditions such as switching speed, on-state duration and load current.

Switching Behavior and Dynamic On-Resistance of Lateral β-Ga2O3 MOSFETs Up to 400 V

A gallium oxide (β-Ga2O3) Schottky barrier diode (SBD) is proposed and characterized. The fabricated diode has an area of 300 μm × 300 μm with a 12 μm unintentionally doped (UID) (1.7 × 1016 cm−3) Ga2O3 epitaxial layer on Sn doped (5.4 × 1018 cm−3) (010) Ga2O3 substrate. The device has 1.02 kV breakdown
voltage and 500 mA forward current at 5.5 V. The reverse recovery characteristic and the rectification capability of the diode are experimentally studied. The Ga2O3 SBD shows a high potential for power device applications such as pulse power applications.

Reverse Recovery and Rectification Characteristic of β-Ga2O3 Schottky Barrier Diode

Higher cost, lack of availability, and higher on-resistance (RDSon) are just a few drawbacks of semiconductor devices at higher voltages. This applies to the wide-bandgap semiconductors like Silicon Carbide (SiC) MOSFETs as well, where individual devices are not commercially available at voltages above 3.3-kV at the time of preparing this paper. Series connection of individual semiconductor devices is an effective way to achieve higher-voltage switches. However, the inherent unequal static and dynamic voltage sharing problems between the devices in the stack need to be addressed. The majority of the existing voltage balancing schemes are developed for slow-switching Si-based semiconductors, and bring about a significant amount of additional losses in the control circuit or on the switches. Some other techniques are not practical on SiC MOSFETs, given the high switching speeds featured by these devices. This paper tries to survey and compare the voltage balancing techniques proposed by researchers for being used on the faster-switching wide-bandgap devices. The voltage balancing techniques proposed in literature are classified into 5 different categories of “passive solutions”, “self-powered and pulse-powered gate drivers”, “active gate control techniques”, “gate timing control methods” and “voltage clamping solutions”. Then, a comprehensive and unbiased comparison is conducted between different voltage balancing techniques from “cost”, “modularity”, “complexity”, “startup balancing”, “losses” and “voltage balancing” points of view. Finally, conclusions from the conducted comparison are discussed.

Study of Voltage Balancing Techniques for Series-Connected Wide-Bandgap Semiconductors Devices

GaN-based transistors offers the highest power density for radio-frequency (RF) applications. However, self-heating significantly limits device performance and reliability that must be managed for the transistors to perform. Exploiting the high thermal conductivity of polycrystalline diamond (300-2000 W/mK near room temperature), we have demonstrated polycrystalline diamond integration on top of the GaN channels for effective device cooling, while preserving its electrical performance. Various thicknesses of polycrystalline diamond were grown on top of the GaN channel to investigate its impact on the device temperature. Using Raman thermometry, a remarkably lower temperature (by 30-60 °C) was measured in the channel for devices with diamond compared to control devices without diamond. The effect of diamond thickness (250-650 nm) and device layout on the heat dissipation was carefully studied and discussed. We have shown that thicker diamond (~650 nm) along with the metal-diamond overlap improves channel cooling capabilities of the diamond heat spreader by a factor of two.

Low Contact Resistance CMOS-Compatible RF GaN-on-Silicon HEMTs

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Investigation on the Accuracy of the VSD-Method for Different SiC MOSFET Designs Considering Different Measurement Parameters

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