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A gallium oxide (β-Ga2O3) Schottky barrier diode (SBD) is proposed and characterized. The fabricated diode has an area of 300 μm × 300 μm with a 12 μm unintentionally doped (UID) (1.7 × 1016 cm−3) Ga2O3 epitaxial layer on Sn doped (5.4 × 1018 cm−3) (010) Ga2O3 substrate. The device has 1.02 kV breakdown
voltage and 500 mA forward current at 5.5 V. The reverse recovery characteristic and the rectification capability of the diode are experimentally studied. The Ga2O3 SBD shows a high potential for power device applications such as pulse power applications.

IEEE WiPDA 2021

Reverse Recovery and Rectification Characteristic of β-Ga2O3 Schottky Barrier Diode

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

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The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

technical paper

This presentation discusses the impacts of the defect densities on SiC epitaxial wafers on the yield and oxide reliability of large area SiC power MOSFETs. TDDB measurements on commercial SiC power MOSFETs with different sizes are conducted to check if oxide reliability degrades with larger device size. The gate oxide reliability of planar and trench SiC power MOSFETs are also studied and compared.

Impacts of Area-Dependent Defects on the Yield and Gate Oxide Reliability of SiC Power MOSFETs

This paper reports the layout approaches and resulting static, dynamic, and short-circuit (SC) ruggedness characteristics of 1.2 kV power MOSFETs fabricated on a 6-inch 4H-SiC substrate. Different layout topologies (linear and hexagonal) and different design variations (with and without bridge of P-well) were investigated to study their effect. It was experimentally demonstrated that 1) the hexagonal layout topology enables a low specific on-resistance (Ron.sp), 2) the linear MOSFET can be utilized in high frequency applications due to fast switching speed, and 3) the hexagonal topology with bridge offers greater reliability and ruggedness.

A Static, Switching, Short-circuit Characteristics of 1.2 kV 4H-SiC MOSFETs: Comparison between Linear and (Bridged) Hexagonal Topology

Enhanced short-circuit (SC) withstand capability for SiC Power MOSFETs has been recently achieved using the BaSIC(DMM) Topology which employs a Gate-Source-Shorted Si Depletion Mode MOSFET (GSS Si DMM) in series with the source of the SiC Power MOSFET. This approach increase SC withstand capability with minimal impact on on-resistance and switching losses. In this paper, it is demonstrated for the first time that the Composite MOSFETs created within the BaSIC(DMM) Topology can be paralleled to increase current and power handling capability while maintaining good SC withstand capability. Experimental results on scaling the power were obtained using Composite MOSFET made with 1.2 kV 280 mΩ Si DMM devices. Excellent linearity of current scaling and SC capability was experimentally achieved with 2, 3 and 4 paralleled composite MOSFETs.

Excellent Static and Dynamic Scaling of Power Handling Capability of the BaSIC(DMM) Topology with 1.2 kV SiC Power MOSFETs

During power cycling tests, a precise junction temperature estimation is necessary for a correct interpretation of the test results and it is even more important, when the test results are used for lifetime modeling. For SiC MOSFETs, a common approach is to use the VSD-Method, which was reported to deliver accurate junction temperature readings. However, given the variety of device designs and technologies available on the market, this cannot be taken for granted for all SiC MOSFETs. For that purpose, different aspects of the accuracy of the VSD-Method were investigated in this work, by comparing the junction temperature reading obtained by the VSD-Method, with the actual chip temperature, measured by thermography for two different SiC MOSFET designs. Whereas one design lead to accurate temperature readings, the other exhibited a significant deviation between the temperature measured by thermography and the temperature reading by the VSD-Method. Furthermore, the impact of the gate voltage on the temperature reading of the VSD-Method was investigated. Both designs exhibit a consistent temperature reading for gate voltages 2V above and below the maximum rated negative gate voltage for a wide range of sensing currents. Hence, the results show, that a systematic measurement error can occur for some SiC MOSFET designs, which may cause a misinterpretation of power cycling test results. Therefore, it is important to verify the accuracy of the temperature estimation when deploying the VSD-Method for SiC MOSFETs, particularly when comparative tests are performed or the test results are used for lifetime modeling.

Investigation on the Accuracy of the VSD-Method for Different SiC MOSFET Designs Considering Different Measurement Parameters

This paper reports about 10kW-class 650V-rated GaN switches. GaN-on-Si HEMTs with maximum current of 780A and 33.2mm2 die area were fabricated by chip scaling and intrinsic device shrink which gave improved RON*A area figure of merit. Tight integration with a low-voltage Si MOSFET results in a cascode switch with a high threshold of 4V, stable dynamic on-resistance of 14 milliohms for up to 750V VDS and single-chip-like simplicity in TO-247 packages. Using a simple gate drive of 0-12V and drive current below 0.7A, the GaN FET exhibits faster switching and 2x lower switching losses than a competing SiC MOSFET. When tested in a 240V:400V half-bridge synchronous boost converter, it was possible to get 12kW output power with >99% peak efficiency at 3kW.

650V/780A GaN Power HEMT Enabling 10kW-Class High-efficiency Power Conversion


This paper presents the evaluation of a 650-V, 100- A, 22-mΩ rated D3GaN (Direct Drive Depletion-mode) power switch (V22TC65S1A) from VisIC Technologies, which is designed for electric vehicles (EV) powertrain inverter applications. The static and dynamic performance as well as the surge-energy and short-circuit robustness of the D3GaN were evaluated in a top- cooled surface-mount device package. Multiple customized test boards were employed to evaluate the switching loss, dynamic on- resistance, gate charge (Qg), and robustness. The D3GaN switch has shown a small total Qg, high breakdown voltage, positive threshold voltage, small switching-energy loss, fast switching speed, and good robustness. These advantages make the D3GaN switch an attractive candidate for high-power EV powertrain inverter applications. To the best of our knowledge, this paper presents the first comprehensive evaluation of a high-power GaN device targeted for EV inverter applications.

Evaluation of 650V, 100A Direct-Drive GaN Power Switch for Electric Vehicle Powertrain Applications

We present a reduced physics-based thermal model to predict the thermal performance of Chip Scale Package (CSP) GaN FETs mounted to printed circuit boards (PCBs) and provide an easy-to-use thermal characterization tool for engineers and designers to quickly assess thermal management strategies. The heat conductance from the GaN FET to both the PCB side and to the “case” (i.e., die exposed surface) are modeled using resistive-network circuit modeling. The thermal resistance in each conductance path is presented for different parameters relating to PCB construction (stack-up, area, via density), FET size, and cooling approach (TIM material, heat spreader and heatsink). A comprehensive set of thermal finite-element simulations was run over the set of parameters. The results, presented in easy “look-up” style graphs, show that even with a small footprint, GaN FETs power-handling capability can be extended when effectively cooled using a simple PCB design and thermal management approach.

Quick Thermal Performance Estimation of Chip Scale Packaged GaN FETs using a Simple Circuit Model

This work reports an on-wafer study of avalanche behavior and failure analysis of in-house fabricated 1.3 kV GaN-on-GaN P-N diodes. DC breakdown is measured at different temperatures to confirm avalanche behavior. Diode’s avalanche
ruggedness is measured directly on-wafer using a modified unclamped inductive switching (UIS) test set-up with an integrated thermal chuck and high-speed CCD for real-time imaging during the test. The avalanche ruggedness of the GaN P-N diode is evaluated and compared with a commercial SiC Schottky diode of similar voltage and current rating. Failure analysis is done using SEM and optical microscopy to gain insight into the diode’s failure mechanism during avalanche operation.

On-Wafer Investigation of Avalanche Robustness in 1.3 kV GaN-on-GaN P-N Diode Under Unclamped Inductive Switching Stress

GaN transistors, and more recently integrated circuits, have been in mass production for over a decade [1] with several manufacturers reporting tens of millions of units shipped with billions of hours in actual end-use applications. The track record has been extraordinarily successful, and one of the key reasons is that GaN devices are far more rugged than their silicon MOSFET ancestors [2].
Recently, Efficient Power Conversion (EPC) did a series of tests to take eGaN FETs beyond their datasheet limits to quantify the effects of large amounts of overstress voltage and current. This paper will examine the results and those tests to show how operation under extreme conditions for long periods of time can be a practical new tool for power system design engineers.

Extreme GaN – What Happens When eGaN® FETs Are Exposed to Voltage Levels Well Above Data Sheet Limits

This paper studies switching behavior and dynamic on-state characteristics of lateral 10 mm depletion-mode β-Ga2O3 met-al-oxide-semiconductor field-effect transistors (MOSFETs). Improvements in device technology and fabrication enable hard-switching operation with an increase of the maximum blocking voltage to 400 V at 0.26 A load current in a double-pulse test configuration. Compared to static measurements, dispersion effects lead to an increased on-resistance in hard-switched operation, which becomes especially pronounced at blocking voltages above 200 V. The extend of dynamic Ron-increase further depends on several operation conditions such as switching speed, on-state duration and load current.

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Impacts of Area-Dependent Defects on the Yield and Gate Oxide Reliability of SiC Power MOSFETs

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