United States

This paper reports the layout approaches and resulting static, dynamic, and short-circuit (SC) ruggedness characteristics of 1.2 kV power MOSFETs fabricated on a 6-inch 4H-SiC substrate. Different layout topologies (linear and hexagonal) and different design variations (with and without bridge of P-well) were investigated to study their effect. It was experimentally demonstrated that 1) the hexagonal layout topology enables a low specific on-resistance (Ron.sp), 2) the linear MOSFET can be utilized in high frequency applications due to fast switching speed, and 3) the hexagonal topology with bridge offers greater reliability and ruggedness.

IEEE WiPDA 2021

A Static, Switching, Short-circuit Characteristics of 1.2 kV 4H-SiC MOSFETs: Comparison between Linear and (Bridged) Hexagonal Topology

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

### Please select the button below to view and download the session papers. The Virtual Proceedings PDF can be downloaded [here.](https://drive.google.com/file/d/171y2_u63V-pc9-bC-eZgHLzJou2oCfST/view?usp=sharing)

[![](https://assets.underline.io/uploads/markdown_image/1/image/c8e1b0a2881d3bb0a75ece4761f43c9f.png)](https://drive.google.com/drive/folders/1GWEFLzH6K4aUBaJiBFJDw4x9sKLTl6-g?usp=sharing)


This event requires a registration to attend, please register [here](https://web.cvent.com/event/536cea3d-4c0d-4d50-8939-529979d80785/summary) to purchase a ticket. 

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

The gate oxide reliability for commercial silicon carbide (SiC) power metal-oxide-semiconductor field-effect-transistors (MOSFETs) is significant for their applications. The constant-voltage time-dependent dielectric breakdown (TDDB)
measurement is commonly utilized to evaluate the dielectric failure time of the SiC power MOSFETs under normal operation. A charge-to-breakdown approach based on the oxide tunneling current behavior has been proposed recently for the projection of dielectric failure time. The method is less time-consuming but
requires the oxide leakage current behavior of the devices to follow a universal envelope. This work compares the predicted failure times of commercial 1.2 kV SiC MOSFETs from the charge-to-breakdown approach and the constant-voltage TDDB
method. The results show that the constant-voltage TDDB method applied under low oxide fields (Eox < 9MV/cm) produces the most conservative prediction of the device lifetime.

Comparison of Gate Oxide Lifetime Predictions with Charge-to-Breakdown Approach and Constant-Voltage TDDB on SiC Power MOSFET

This presentation discusses the impacts of the defect densities on SiC epitaxial wafers on the yield and oxide reliability of large area SiC power MOSFETs. TDDB measurements on commercial SiC power MOSFETs with different sizes are conducted to check if oxide reliability degrades with larger device size. The gate oxide reliability of planar and trench SiC power MOSFETs are also studied and compared.

Impacts of Area-Dependent Defects on the Yield and Gate Oxide Reliability of SiC Power MOSFETs

The presentation shows a submodule design for a 2 kV, 1 MW integrated modular motor drive (IMMD) for aviation applications. IMMD system and submodule structures are illustrated and the design challenges are introduced. The gate drive design, busbar design and partial disharge (PD) related studies for the submodule are discussed in detail. The submodule testing results are presented at the end. Double-pulse, short-circuit, and H-bridge test results validated the electrical performance of the sub-module. Preliminary PD tests show that the submodule is free of PD at low pressure of 87 Torr, which is the air pressure at 50,000 feet above the sealevel. The full scale inverter formed by these submodules is expected to achieve an efficiency over 99% with a power density of 35.36 kW/kg.

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Comparison of Gate Oxide Lifetime Predictions with Charge-to-Breakdown Approach and Constant-Voltage TDDB on SiC Power MOSFET

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