France

A semiconductor laser can be modeled as a current controlled oscillator since it can be tuned using its gain section current. Therefore, a semiconductor laser can be phase and frequency locked to a reference laser using an electro-optical phase locked loop (EOPLL). In this talk, some of the EOPLL design challenges such as the effect of the loop delay and laser FM response will be discussed and applications of EOPLLs in optical synthesis and coherent communication will be presented.

ESSCIRC ESSDERC Educational Events

Relative Phase Control of Lasers; From Optical Synthesis to Coherent Communication

optical frequency synthesis

electro-optical phase locked loops

integrated photonics

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

This work presents an in-package D-band wireless module co-integrating an innovative channel-bonding transmitter IC in 45 nm CMOS PDSOI technology and a patch antenna fabricated using a low-cost printed circuit board process. The transmitter is composed of two up-conversion chains with dedicated millimeter-wave local oscillator generators and operates over contiguous sub-bands around 147.96 GHz. The two sub-band signals are combined off-chip using a substrate integrated waveguide diplexer and radiated by a four-patch antenna array realized on the same laminate substrate. The total output band spans from 139.3 to 156.6 GHz. A data rate of 84.48 Gb/s is demonstrated using 64-QAM.

D-band on GF 45RFSOI

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we will review the development of partially depleted 200 mm & 300 mm RF SOI technologies developed at STMicroelectronics to address 5G Front End Module (mainly RF switches and Low Noise Amplifiers) and new requirements implied by 6G enablement.

Advanced 200 mm and 300 mm RF SOI Technologies Targeting 5G and beyond (6G) RF Front End Module SOC

Performances of RF and millimeter-wave integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future low power wireless communication systems operating in the millimeter-wave range. Innovation pathways of the FD SOI technology to fulfill the requirements of millimeter-wave wireless systems will be discussed, i.e. channel engineering or metal gate at the transistor level, and smart PN junction implants combined with high-resistivity Si base or the silicon porosification at the substrate level. The importance of a powerful simulation tool to save silicon runs, and thus time and cost, will be highlighted.

Next generation of FD SOI platform to fulfill the requirements of millimeter-wave wireless systems

The research area of improving the performance, cost, and size of RF solutions for 5G LTE is very active with many developments which shapes the semiconductor industry evolution. Mobile cellular subscribers are expected to reach more than 6.5 billion by 2021 and 5G LTE will bring high data capacity as well as low latency using sub-6GHz and mm-Wave spectrum. The short course presents the status of 5G LTE RF Front End (RFFE) techniques to deliver an over gigabit-per-second data rate such as Carrier Aggregation, MIMO as well Wider Modulation Bandwidth for LTE and mm-Wave spectrum. 
The RFFEs will integrate power amplifiers, switches, couplers, tuners, and active acoustic filters. The workshop will cover practical design aspects for 5G FEMS with emphasis for FEM architectures, power amplifiers, switches, and active filters as well the technologies involved into these designs. The workshop will also cover aspects of new 5G LTE integration for envelope tracking and LNA design. 5G LTE New Radio (NR) will increase the complexity for RFFEs and will be covered in this workshop .



Next gen 5G RF Front End challenges

Demand for better wireless signals has increased with larger networks and connected devices. Wi-Fi has also increased in speed, allowing more connections through improvements in frequency used and data transmission. The enhancements for Wi-Fi 6 impose new design challenges. One of the requirements is on the amplifier section where higher linearity and a flatter response curve is necessary. Accomplishing this requires better designed RF components. Another challenge is efficiency and thermal considerations. More advanced processing and RF requires power and creates heat, and building wireless equipment into a compact pleasing form-factor makes thermal management more difficult. The smaller size and lower cost require the IC and packaging technologies to move to a higher level of integration, leading to increased integration complexity.
In this talk, the design challenges for the integration of High-Power Wi-Fi 5/6 Front End Module using advanced package approaches like Fan-Out Wafer-Level Packaging is presented. As an example, PA/Package co-design methodology is described on a High Power SOI-CMOS PA module for 2.4GHz WiFi 6 applications.


Addressing design challenges in High-Power Wi-Fi 5/6 Front End Modules

The hardware in fiber-optic communication typically consists of multiple chips in dedicated optical and electronic technologies packaged together.
While this approach leads to excellent performance, it is not as cost-effective compared to having both optics and electronics integrated on a single chip.
From this perspective, bulk CMOS technology is arguably the most cost-effective integrated platform available, though is not very well suited for optics.
Nevertheless, there have been multiple demonstrations of gigabit fully-integrated fiber-optic receivers in bulk CMOS, even for the telecom wavelengths with an energy below the silicon band gap.
In this talk we delve deeper in the relevant optical photodetector devices, as well as the circuits involved to realize such opto-electric integrated circuits.

Fiber-Optic Receivers in Bulk CMOS - More than just pn-diodes

Many smart-power, medical and power applications require full galvanic isolation between various power domains. Traditionally this isolation is accomplished by capacitive coupling, magnetic coupling or by optocoupling that all have their specific pros and cons. In this talk, the focus is on single-chip fully integrated opto-coupling in a commercial CMOS technology, aiming at smart power applications. Firstly the physics behind light generation and light detection in silicon are reviewed, which leads to a number of challenges for silicon-integrated opto-coupling systems. Secondly a number of solutions for these challenges are presented, at layout, device, circuit and system level that, combined, enable opto-couplers in commercial SOI CMOS technology. Lastly, measurement results are discussed.

Optocoupling in CMOS

Thick, reach-through CMOS SPADs will be introduced, which possess a large photon detection probability (PDP) for red and near-infrared wavelengths. Circuits for fast active quenching and reduction of afterpulsing will be shown. In addition, quenchers for excess biases up to four times the nominal supply voltage will be described. Furthermore, an outstanding model for PDP calculation inclusive optical transmission in isolation and passivation stacks will be presented. First results of thick-SPAD sensors in TOF applications will be added.

Thick SPADs and Readout Circuits for High Excess Bias

This presentatio in an introduction to Silicon Photonics for Datacommunication.
Objective is be to review the basics of Silicon Photonics : optical interconnects in datacenter, datarate evolution, the interest of silicon photonics, basic process and main devices physics.


An introduction to Silicon Photonics for Datacommunication

For a long time, there was high expectation of being able to integrate monolithically photonic devices on a single chip, following the path traced by the microelectronics industry.
Unfortunately, process complexity to manufacture photonic chips prevent large-scale production of PICs and the industry remained focused on the single components.
Nowadays the technology allows high level of integration to target a wide variety of applications through the standardization of photonic integration processes for InP and the introduction of process design kits.


Relative Phase Control of Lasers; From Optical Synthesis to Coherent Communication

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Relative Phase Control of Lasers; From Optical Synthesis to Coherent Communication

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D-band on GF 45RFSOI

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Wide Dynamic Range Multichannel Lock-in Amplifier for Contactless Optical Sensors with Sub-Ps Resolution

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PRESENTATIONS

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RESOURCES

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