France

This work presents an in-package D-band wireless module co-integrating an innovative channel-bonding transmitter IC in 45 nm CMOS PDSOI technology and a patch antenna fabricated using a low-cost printed circuit board process. The transmitter is composed of two up-conversion chains with dedicated millimeter-wave local oscillator generators and operates over contiguous sub-bands around 147.96 GHz. The two sub-band signals are combined off-chip using a substrate integrated waveguide diplexer and radiated by a four-patch antenna array realized on the same laminate substrate. The total output band spans from 139.3 to 156.6 GHz. A data rate of 84.48 Gb/s is demonstrated using 64-QAM.

ESSCIRC ESSDERC Educational Events

D-band on GF 45RFSOI

45nm rfsoi

d-band

transmitter

cmos

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

Biological networks of neurons and synapses have the capacity to process multiple operations through short electrical pulses, also referred to as “spikes”, with very low energy consumption. Spiking Neural Networks (SNN) are a new form of Artificial Intelligence (AI) that aim to replicate these cognitive features in order to improve next generation computer’s performance. We present the design and simulation of an individual spiking laser to be used as a photonic neuron for a SNN scale-up. The neuron is a semiconductor laser optimized for pulsed operation through modification of the CEA Leti III-V on Si integrated continuous wave laser's heterostructure. A first demonstration of its neural features connected with synaptic functions is also reported.

Pulsed lasers neurons integrated on silicon for dense spiking neural network

LEDs for the UV-C spectral range gained increased attention in the recent years due to potential applications regarding the CoVID-19 pandemic. While its wide commercial uptake of UV-C LEDs is still inhibited by their relatively small efficiencies and lifetimes compared to conventional UV-light sources and compared to LEDs emitting in the visible spectral range, many improvements in the semiconductor device (LED chip and package) performance yield an accelerated entry into various markets.
The presentation will highlight the improvements enabling the achieved significant improvements in UV-C LEDs, such as crystalline quality of the chips, operation voltage, output power, lifetime and stability of their fabrication processes. 
The major application for UV-C LEDs is the large field of UV disinfection due to their UV-C radiation. Beyond this there are various other application fields. In the past years UV LEDs successfully entered other applications like streetlighting, horticulture lighting and general lighting. It always started as the underdog and a direct comparison with conventional sources was difficult and barely in the benefit of the new source. But again, the completely different properties of LED light sources are showing significant benefits in new system designs which have not been possible before.
Benefits of distinct UV-C LED sources and arrangements in different systems will be presented by explaining the features which enable the light source to be competitive and even perfectly suited for various disinfection applications.


Deep UV LEDs and its Applications

While digital synthesis has progressed enormously over the past decades, the synthesis of the analog and mixed-signal circuits has been lagging behind. Despite enormous progress in optimization methods for both analog circuit sizing and analog layout generation, adoption in daily industrial practice has been quite limited. Yet, the growing complexity of integrated systems to be designed today and the growing range of layout constraints introduced by advanced CMOS technologies at 16nm and below increase the need for efficient automated solutions. Also the verification of the designs becomes extremely challenging. Fortunately, novel algorithmic developments, including techniques from machine learning and artificial intelligence, provide the boost towards analog synthesis with increased functionality. Starting from an historical perspective, this presentation will sketch novel developments that aim to boost analog synthesis to the level desired in industrial practice.

Analog IC synthesis: the return of the Jedi

At ICCAD20, Tim from Google presented the paper titled "The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts" documenting roadblocks preventing fully open source ICs creation.

In less than a year the world has already rapidly changed thanks to Google releasing a fully open source, manufacturable 130nm PDK with open source tooling and no-cost MPW shuttle program! 

This talk will cover the success of Google investments in the open source IC space and the resulting huge explosion in open down to the transistor IC parts (including all of the RTL, tooling & PDK). It will also include exciting new annoucements and how new people can get involved.

Fully open source, manufacturable, PDK for 130nm process with fully open source tooling AND no-cost MPW shuttle program!

In order to truly unleash the productivity benefits offered by programmatic approaches to analog / custom circuit design, the analog designers themselves (as well as their managers) will need to not only be convinced that they should take this kind of approach, but in many cases, learn an entirely new set of skills, techniques, and approaches. In this talk, I will therefore offer perspectives gained through both industry and academia on how this seemingly obvious statement has and/or should drive the development/features of the frameworks/methodologies themselves, why I believe this drives us towards generator-based approaches as opposed to automation in the traditional sense, and some key next steps / objectives for the community.

Turning Analog Designers into Analog Generator Writers (and Users)

This presentation introduces a design methodology that is used by Infineon Technologies to automatically generate tape-out compliant analog circuits starting from the design requirements. The flow includes circuit sizing, layout and post-extraction verification, and can be applied to any process technology. We provide an example of its application to the generation of voltage regulators (VR), explain how the algorithms included in the flow handle various specification sets and showcase two different generated layouts.


ANAGEN: A Methodology for ANAlog Circuit GENeration

This talk presents a designer-friendly approach to produce custom layouts in advanced DRAM technologies. Memory system designs still rely on full-custom methodologies that manually produce circuit components and layouts for extreme performance optimization and area utilization, rather than exploiting automatic synthesis and place-and-route. However, as the device technology scales down, it becomes significantly challenging to produce custom layouts that meet all complicated design rule constraints. Therefore, an automated layout generation methodology is strongly required to enhance design productivity. While the automatically generated layouts from the methodology should meet all area and design constraints, the methodology should be organized to be readily adopted by circuit designers to utilize their expertise. In this talk, an automatic layout generation engine called layout with gridded objects (LAYGO) is presented, which produces DRC-clean layouts by combining handcrafted or PCell-based primitive templates and grid-based placement and routing functions. In this way, circuit designers can easily create their own layout generators with a minimum level of programming skills. A layout generation example in an advanced DRAM technology is presented, which produces >300 logic circuits instantly in a new technology node, which yields a >5x improvement in design productivity.

Applying automated design methodologies to advanced DRAM technologies

This talk describes a modular programmatic approach for design and verification of analog building blocks for utility circuits and Analog-to-digital converters. Use of programmatic design methodologies brings changes to organization of circuit design and verification. In this talk we describe practical aspects on how to take the programmatic methodology into use gradually in the organization. We demonstrate the use of Berkeley Analog Generator (BAG) for layout generation with vendor provided, already available device generators to reduce the configuration overhead, combined with modular design configuration to streamline re-use of the generators. Furthermore, we describe the verification methodology based on TheSyDeKick, a unified multi-mode modeling and verification environment that connects system models, digital RTL and analog circuit models in verification independently of whether they come from generators or more conventional design flows. We present the use of these methodologies in design of building blocks for time-based AD converters with circuit optimization examples.

Modular programmatic design and verification methodology for analog circuits in ADCs

5G and Beyond 5G applications are driving research towards highly integrated PA modules with multiband capabilities. Multiband requirements, along with the need for reduced power consumption, make the PA design highly critical since high PAPR signals require the PA to be backed-off from its peak power in order to achieve the necessary system linearity. This calls for an important shift from traditional PA design to more advanced PA architectures capable of handling signals with high PAPR while maintaining high efficiency and linearity on a broad frequency range. In addition, achieving high performance and reliability while maintaining compact size requires innovative thermal and electromagnetic management schemes. In this talk, I will give an overview of the challenges, recent progress and trends related to the integration of high efficiency PA design in RF-SOI technology for mobile applications operating below 6GHz.

High-Efficiency Power Amplifiers in RF-SOI technology: Challenges, Progress and Perspectives

Recent advancements and applications in compact phased arrays, MIMO basestations and handsets, automotive radar, etc. are driving the need for RF power generation in CMOS technologies to accomodate high complexity systems that require RF output power. This presentation will provide an overview of CMOS device concepts up to architectural choices that have been proposed to improve RF power and efficiency in CMOS technologies. This discussion focuses on RF power amplifier concepts.

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Pulsed lasers neurons integrated on silicon for dense spiking neural network

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Next from ESSCIRC ESSDERC Educational Events

Pulsed lasers neurons integrated on silicon for dense spiking neural network

Similar lecture

A 253-280 GHz Wide Tuning Range VCO with -3.5 dBm Peak Output Power in 40-nm CMOS

Stay up to date with the latest Underline news!

PRESENTATIONS

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COMPANY

RESOURCES

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