France

Many smart-power, medical and power applications require full galvanic isolation between various power domains. Traditionally this isolation is accomplished by capacitive coupling, magnetic coupling or by optocoupling that all have their specific pros and cons. In this talk, the focus is on single-chip fully integrated opto-coupling in a commercial CMOS technology, aiming at smart power applications. Firstly the physics behind light generation and light detection in silicon are reviewed, which leads to a number of challenges for silicon-integrated opto-coupling systems. Secondly a number of solutions for these challenges are presented, at layout, device, circuit and system level that, combined, enable opto-couplers in commercial SOI CMOS technology. Lastly, measurement results are discussed.

ESSCIRC ESSDERC Educational Events

Optocoupling in CMOS

silicon photodiode

avalanche

silicon led

optocoupler

cmos

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

This talk presents a designer-friendly approach to produce custom layouts in advanced DRAM technologies. Memory system designs still rely on full-custom methodologies that manually produce circuit components and layouts for extreme performance optimization and area utilization, rather than exploiting automatic synthesis and place-and-route. However, as the device technology scales down, it becomes significantly challenging to produce custom layouts that meet all complicated design rule constraints. Therefore, an automated layout generation methodology is strongly required to enhance design productivity. While the automatically generated layouts from the methodology should meet all area and design constraints, the methodology should be organized to be readily adopted by circuit designers to utilize their expertise. In this talk, an automatic layout generation engine called layout with gridded objects (LAYGO) is presented, which produces DRC-clean layouts by combining handcrafted or PCell-based primitive templates and grid-based placement and routing functions. In this way, circuit designers can easily create their own layout generators with a minimum level of programming skills. A layout generation example in an advanced DRAM technology is presented, which produces >300 logic circuits instantly in a new technology node, which yields a >5x improvement in design productivity.

Applying automated design methodologies to advanced DRAM technologies

This talk describes a modular programmatic approach for design and verification of analog building blocks for utility circuits and Analog-to-digital converters. Use of programmatic design methodologies brings changes to organization of circuit design and verification. In this talk we describe practical aspects on how to take the programmatic methodology into use gradually in the organization. We demonstrate the use of Berkeley Analog Generator (BAG) for layout generation with vendor provided, already available device generators to reduce the configuration overhead, combined with modular design configuration to streamline re-use of the generators. Furthermore, we describe the verification methodology based on TheSyDeKick, a unified multi-mode modeling and verification environment that connects system models, digital RTL and analog circuit models in verification independently of whether they come from generators or more conventional design flows. We present the use of these methodologies in design of building blocks for time-based AD converters with circuit optimization examples.

Modular programmatic design and verification methodology for analog circuits in ADCs

5G and Beyond 5G applications are driving research towards highly integrated PA modules with multiband capabilities. Multiband requirements, along with the need for reduced power consumption, make the PA design highly critical since high PAPR signals require the PA to be backed-off from its peak power in order to achieve the necessary system linearity. This calls for an important shift from traditional PA design to more advanced PA architectures capable of handling signals with high PAPR while maintaining high efficiency and linearity on a broad frequency range. In addition, achieving high performance and reliability while maintaining compact size requires innovative thermal and electromagnetic management schemes. In this talk, I will give an overview of the challenges, recent progress and trends related to the integration of high efficiency PA design in RF-SOI technology for mobile applications operating below 6GHz.

High-Efficiency Power Amplifiers in RF-SOI technology: Challenges, Progress and Perspectives

Recent advancements and applications in compact phased arrays, MIMO basestations and handsets, automotive radar, etc. are driving the need for RF power generation in CMOS technologies to accomodate high complexity systems that require RF output power. This presentation will provide an overview of CMOS device concepts up to architectural choices that have been proposed to improve RF power and efficiency in CMOS technologies. This discussion focuses on RF power amplifier concepts.

Overview of RF Power Generation Using CMOS Technologies

This work presents an in-package D-band wireless module co-integrating an innovative channel-bonding transmitter IC in 45 nm CMOS PDSOI technology and a patch antenna fabricated using a low-cost printed circuit board process. The transmitter is composed of two up-conversion chains with dedicated millimeter-wave local oscillator generators and operates over contiguous sub-bands around 147.96 GHz. The two sub-band signals are combined off-chip using a substrate integrated waveguide diplexer and radiated by a four-patch antenna array realized on the same laminate substrate. The total output band spans from 139.3 to 156.6 GHz. A data rate of 84.48 Gb/s is demonstrated using 64-QAM.

D-band on GF 45RFSOI

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we will review the development of partially depleted 200 mm & 300 mm RF SOI technologies developed at STMicroelectronics to address 5G Front End Module (mainly RF switches and Low Noise Amplifiers) and new requirements implied by 6G enablement.

Advanced 200 mm and 300 mm RF SOI Technologies Targeting 5G and beyond (6G) RF Front End Module SOC

Performances of RF and millimeter-wave integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future low power wireless communication systems operating in the millimeter-wave range. Innovation pathways of the FD SOI technology to fulfill the requirements of millimeter-wave wireless systems will be discussed, i.e. channel engineering or metal gate at the transistor level, and smart PN junction implants combined with high-resistivity Si base or the silicon porosification at the substrate level. The importance of a powerful simulation tool to save silicon runs, and thus time and cost, will be highlighted.

Next generation of FD SOI platform to fulfill the requirements of millimeter-wave wireless systems

The research area of improving the performance, cost, and size of RF solutions for 5G LTE is very active with many developments which shapes the semiconductor industry evolution. Mobile cellular subscribers are expected to reach more than 6.5 billion by 2021 and 5G LTE will bring high data capacity as well as low latency using sub-6GHz and mm-Wave spectrum. The short course presents the status of 5G LTE RF Front End (RFFE) techniques to deliver an over gigabit-per-second data rate such as Carrier Aggregation, MIMO as well Wider Modulation Bandwidth for LTE and mm-Wave spectrum. 
The RFFEs will integrate power amplifiers, switches, couplers, tuners, and active acoustic filters. The workshop will cover practical design aspects for 5G FEMS with emphasis for FEM architectures, power amplifiers, switches, and active filters as well the technologies involved into these designs. The workshop will also cover aspects of new 5G LTE integration for envelope tracking and LNA design. 5G LTE New Radio (NR) will increase the complexity for RFFEs and will be covered in this workshop .



Next gen 5G RF Front End challenges

Demand for better wireless signals has increased with larger networks and connected devices. Wi-Fi has also increased in speed, allowing more connections through improvements in frequency used and data transmission. The enhancements for Wi-Fi 6 impose new design challenges. One of the requirements is on the amplifier section where higher linearity and a flatter response curve is necessary. Accomplishing this requires better designed RF components. Another challenge is efficiency and thermal considerations. More advanced processing and RF requires power and creates heat, and building wireless equipment into a compact pleasing form-factor makes thermal management more difficult. The smaller size and lower cost require the IC and packaging technologies to move to a higher level of integration, leading to increased integration complexity.
In this talk, the design challenges for the integration of High-Power Wi-Fi 5/6 Front End Module using advanced package approaches like Fan-Out Wafer-Level Packaging is presented. As an example, PA/Package co-design methodology is described on a High Power SOI-CMOS PA module for 2.4GHz WiFi 6 applications.


Addressing design challenges in High-Power Wi-Fi 5/6 Front End Modules

The hardware in fiber-optic communication typically consists of multiple chips in dedicated optical and electronic technologies packaged together.
While this approach leads to excellent performance, it is not as cost-effective compared to having both optics and electronics integrated on a single chip.
From this perspective, bulk CMOS technology is arguably the most cost-effective integrated platform available, though is not very well suited for optics.
Nevertheless, there have been multiple demonstrations of gigabit fully-integrated fiber-optic receivers in bulk CMOS, even for the telecom wavelengths with an energy below the silicon band gap.
In this talk we delve deeper in the relevant optical photodetector devices, as well as the circuits involved to realize such opto-electric integrated circuits.

Optocoupling in CMOS

Downloads

Next from ESSCIRC ESSDERC Educational Events

Applying automated design methodologies to advanced DRAM technologies

Similar lecture

A 253-280 GHz Wide Tuning Range VCO with -3.5 dBm Peak Output Power in 40-nm CMOS

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Optocoupling in CMOS

.css-70qvj9{display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-align-items:center;-webkit-box-align:center;-ms-flex-align:center;align-items:center;}Downloads

Next from ESSCIRC ESSDERC Educational Events

Applying automated design methodologies to advanced DRAM technologies

Similar lecture

A 253-280 GHz Wide Tuning Range VCO with -3.5 dBm Peak Output Power in 40-nm CMOS

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Downloads