France

This talk presents a designer-friendly approach to produce custom layouts in advanced DRAM technologies. Memory system designs still rely on full-custom methodologies that manually produce circuit components and layouts for extreme performance optimization and area utilization, rather than exploiting automatic synthesis and place-and-route. However, as the device technology scales down, it becomes significantly challenging to produce custom layouts that meet all complicated design rule constraints. Therefore, an automated layout generation methodology is strongly required to enhance design productivity. While the automatically generated layouts from the methodology should meet all area and design constraints, the methodology should be organized to be readily adopted by circuit designers to utilize their expertise. In this talk, an automatic layout generation engine called layout with gridded objects (LAYGO) is presented, which produces DRC-clean layouts by combining handcrafted or PCell-based primitive templates and grid-based placement and routing functions. In this way, circuit designers can easily create their own layout generators with a minimum level of programming skills. A layout generation example in an advanced DRAM technology is presented, which produces &gt;300 logic circuits instantly in a new technology node, which yields a &gt;5x improvement in design productivity.

ESSCIRC ESSDERC Educational Events

Applying automated design methodologies to advanced DRAM technologies

dram

layout

automation

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





This talk presents a designer-friendly approach to produce custom layouts in advanced DRAM technologies. Memory system designs still rely on full-custom methodologies that manually produce circuit components and layouts for extreme performance optimization and area utilization, rather than exploiting automatic synthesis and place-and-route. However, as the device technology scales down, it becomes significantly challenging to produce custom layouts that meet all complicated design rule constraints. Therefore, an automated layout generation methodology is strongly required to enhance design productivity. While the automatically generated layouts from the methodology should meet all area and design constraints, the methodology should be organized to be readily adopted by circuit designers to utilize their expertise. In this talk, an automatic layout generation engine called layout with gridded objects (LAYGO) is presented, which produces DRC-clean layouts by combining handcrafted or PCell-based primitive templates and grid-based placement and routing functions. In this way, circuit designers can easily create their own layout generators with a minimum level of programming skills. A layout generation example in an advanced DRAM technology is presented, which produces >300 logic circuits instantly in a new technology node, which yields a >5x improvement in design productivity.

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

In the last 15 years, Fondazione Bruno Kessler (FBK) has developed a custom technology for single-photon avalanche diodes (SPADs) and silicon photomultipliers (SiPMs) optimized for several applications, from high-energy physics experiments to medical imaging or light detection and ranging (LiDAR). In the IPCEI framework, FBK is upgrading its microfabrication facility for the realization of 3D integrated radiation sensors. In the specific case of SiPMs, 3D integration technologies will allow to improve its capabilities by using back side illuminated (BSI) devices and Through Silicon Vias (TSV) interconnections. The BSI approach for SiPMs can be exploited to improve the current photon detection efficiency (PDE), even in the wavelength ranges far away from the visible spectrum, where typically it drops down to about 10% for the near infrared (NIR) and about 15% for vacuum ultraviolet (VUV). A first batch of BSI SiPMs for NIR detection was recently fabricated at FBK as a proof of concept. After wafer bonding and thinning, the characterization results showed an increase of the PDE of about 50% at 900 nm for BSI sensors with metal reflectors compared with the standard front side illuminated (FSI) technology. Research on the realization of the fabrication process modules optimized for near ultraviolet (NUV) and VUV BSI SiPMs is currently ongoing and will also be presented and discussed.

Back side illuminated SiPM from NIR to NUV light detection

Requirements towards chip separation are getting more and more complex in recent years. The increasing trend for lower chip thickness and different backside metal stacks leads to a big variety in processes and material combinations interacting with each other. Unwanted interactions can even block the overall manufacturing flow of chips in module or package assembly.
With the newly presented method on chip level it is now possible to measure in detail the release process of chip from the dicing tape during pick-up and to determine the influence of unit processes like dicing or UV irradiation and their interaction effects on the die bond process during assembly. In this presentation we will focus on the effect of different stress release processes and show the effect of different UV chambers on the UV curing of dicing tapes.

Characterization of Preassembly influence on Die Attach process

LYNRED product offer covers a large span of applications, in cooled and uncooled infrared domains. The presentation will focus on two detectors addressing two different infrared technologies:
 First - « Key elements for hybridization technology development of 2000x2000 pixels Infrared Focal Plane Arrays”..
 Then a LWIR camera module will be presented: an uncooled bolometers detector stacked with a custom IR image processor (ISP). The ISP is a dedicated ASIC built to apply a pipeline of image processing algorithms to the raw sensor data which corrects for pixel defects and non-uniformities in the sensor, without requiring to an external mechanical shutter. With this approach, LYNRED demonstrates an easy-to-use, plug-and-play solution


Lynred Advanced Developments in the Field of Infrared Imaging Technologies

For more than 50 years, Moore's Law has been driven by resolution improvements of lithography scanners which generate an image of the lithography mask on the semiconductor wafer. This image contains the patterning information needed to build up an integrated circuit.
The latest scanner generation uses 13.5 nm light at 0.33NA. Since the last 2 years they are now essential to produce leading edge semiconductor devices. To further increase the resolution ZEISS is working on next generation EUV optics. This optics consists of a highly flexible illumination system and projection optics with NA 0.55 enabling single-exposure sub 8nm half-pitch resolution to allow scaling beyond the next decade.
In this presentation we will explain the system design of the high-NA optical column and we will report on the manufacturing status of mirrors and frames. Furthermore, the buildup of the infrastructure including mirror polishing, coating, surface figure metrology, mirror handling, and integration tooling will be shown.

High NA EUV optics: preparing lithography for the next big step

Biological networks of neurons and synapses have the capacity to process multiple operations through short electrical pulses, also referred to as “spikes”, with very low energy consumption. Spiking Neural Networks (SNN) are a new form of Artificial Intelligence (AI) that aim to replicate these cognitive features in order to improve next generation computer’s performance. We present the design and simulation of an individual spiking laser to be used as a photonic neuron for a SNN scale-up. The neuron is a semiconductor laser optimized for pulsed operation through modification of the CEA Leti III-V on Si integrated continuous wave laser's heterostructure. A first demonstration of its neural features connected with synaptic functions is also reported.

Pulsed lasers neurons integrated on silicon for dense spiking neural network

LEDs for the UV-C spectral range gained increased attention in the recent years due to potential applications regarding the CoVID-19 pandemic. While its wide commercial uptake of UV-C LEDs is still inhibited by their relatively small efficiencies and lifetimes compared to conventional UV-light sources and compared to LEDs emitting in the visible spectral range, many improvements in the semiconductor device (LED chip and package) performance yield an accelerated entry into various markets.
The presentation will highlight the improvements enabling the achieved significant improvements in UV-C LEDs, such as crystalline quality of the chips, operation voltage, output power, lifetime and stability of their fabrication processes. 
The major application for UV-C LEDs is the large field of UV disinfection due to their UV-C radiation. Beyond this there are various other application fields. In the past years UV LEDs successfully entered other applications like streetlighting, horticulture lighting and general lighting. It always started as the underdog and a direct comparison with conventional sources was difficult and barely in the benefit of the new source. But again, the completely different properties of LED light sources are showing significant benefits in new system designs which have not been possible before.
Benefits of distinct UV-C LED sources and arrangements in different systems will be presented by explaining the features which enable the light source to be competitive and even perfectly suited for various disinfection applications.


Deep UV LEDs and its Applications

While digital synthesis has progressed enormously over the past decades, the synthesis of the analog and mixed-signal circuits has been lagging behind. Despite enormous progress in optimization methods for both analog circuit sizing and analog layout generation, adoption in daily industrial practice has been quite limited. Yet, the growing complexity of integrated systems to be designed today and the growing range of layout constraints introduced by advanced CMOS technologies at 16nm and below increase the need for efficient automated solutions. Also the verification of the designs becomes extremely challenging. Fortunately, novel algorithmic developments, including techniques from machine learning and artificial intelligence, provide the boost towards analog synthesis with increased functionality. Starting from an historical perspective, this presentation will sketch novel developments that aim to boost analog synthesis to the level desired in industrial practice.

Analog IC synthesis: the return of the Jedi

At ICCAD20, Tim from Google presented the paper titled "The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts" documenting roadblocks preventing fully open source ICs creation.

In less than a year the world has already rapidly changed thanks to Google releasing a fully open source, manufacturable 130nm PDK with open source tooling and no-cost MPW shuttle program! 

This talk will cover the success of Google investments in the open source IC space and the resulting huge explosion in open down to the transistor IC parts (including all of the RTL, tooling & PDK). It will also include exciting new annoucements and how new people can get involved.

Fully open source, manufacturable, PDK for 130nm process with fully open source tooling AND no-cost MPW shuttle program!

In order to truly unleash the productivity benefits offered by programmatic approaches to analog / custom circuit design, the analog designers themselves (as well as their managers) will need to not only be convinced that they should take this kind of approach, but in many cases, learn an entirely new set of skills, techniques, and approaches. In this talk, I will therefore offer perspectives gained through both industry and academia on how this seemingly obvious statement has and/or should drive the development/features of the frameworks/methodologies themselves, why I believe this drives us towards generator-based approaches as opposed to automation in the traditional sense, and some key next steps / objectives for the community.

Turning Analog Designers into Analog Generator Writers (and Users)

This presentation introduces a design methodology that is used by Infineon Technologies to automatically generate tape-out compliant analog circuits starting from the design requirements. The flow includes circuit sizing, layout and post-extraction verification, and can be applied to any process technology. We provide an example of its application to the generation of voltage regulators (VR), explain how the algorithms included in the flow handle various specification sets and showcase two different generated layouts.


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Next from ESSCIRC ESSDERC Educational Events

Back side illuminated SiPM from NIR to NUV light detection

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Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

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