France

Requirements towards chip separation are getting more and more complex in recent years. The increasing trend for lower chip thickness and different backside metal stacks leads to a big variety in processes and material combinations interacting with each other. Unwanted interactions can even block the overall manufacturing flow of chips in module or package assembly.
With the newly presented method on chip level it is now possible to measure in detail the release process of chip from the dicing tape during pick-up and to determine the influence of unit processes like dicing or UV irradiation and their interaction effects on the die bond process during assembly. In this presentation we will focus on the effect of different stress release processes and show the effect of different UV chambers on the UV curing of dicing tapes.

ESSCIRC ESSDERC Educational Events

Characterization of Preassembly influence on Die Attach process

needle-height

ejection

pickup

preassembly

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

To address the increasingly challenging requirements of the RF front-end (RFFE) for 5G and also anticipated requirements for 6G, the 3D heterogeneous integration of GaN HEMT coupons on a RF-SOI technology is sought for combining the advantages of a high performance RF component and a capable Si based platform. Integration is performed at the transistor level rather than at a functional block level with conventional packaging methods. High performance RF passives, analogue, digital, and I/O functionality is performed by a 130nm RF-SOI technology with Cu and thick Cu metallurgy. GaN HEMT devices are instantiated as necessary to achieve design targets. Several examples of design innovation have been recently demonstrated by X-FAB including a 5.9-7.1GHz High-Linearity LNA, where the first stage cascode combines a HEMT and a Si NMOS exploiting higher output power and linearity of GaN. The second example is a SPST switch, where reduced insertion losses were observed in comparison to GaN on Si as a benefit of the integration method and also a significantly larger power handling capability than a Si counterpart. This discussion will include the present status and remarks on the future of this enabling technology.

multi-technology wafer level integration for RFFE applications

Both in Mobile and High-performance Computing (HPC) applications, efficient power supply of the processors was and is still being a big challenge for designers. Indeed, for these applications the power consumption is increasing while the power supply voltage is decreasing in alignment with the latest technological scaling. Thus, lowering and flattening the Power Distribution Network (PDN) impedance is more than ever important to mitigate the voltage fluctuation, the resonance and anti-resonance peaks caused by the PDN’s components. Such optimization is done by tuning the features of the different decoupling capacitors used along the power path from the power supply down to the processor. In this presentation, the benefits of using Low ESL silicon capacitors are demonstrated and compared to existing classical decoupling solutions. These components bring unprecedented design flexibility and significant improvements by reducing the voltage drop and enabling very low and flat PDN impedance.

Low ESL Ultra-thin silicon capacitors for PDN applications

Microelectronics plays a key role in fighting against global warming and preparing the world for the “post carbon age”. The performance of novel electronic based systems is constantly increasing by consuming less energy. This can be only achieved by novel systems that are designed in a holistic approach (Chip, passive components, package). The electronic package and interconnect solutions are contributing to these goals in a significant way. Besides this product focused potential for green electronics production and manufacturing of those is offering significant potential as well. Novel methods with respect to sustainable manufacturing have been achieved in this field and is contributing to reduce resource consumption in during production of electronic based systems of the future. These novel PCB and Packaging solutions as well as sustainable production concepts for them are under development in AT&S under IPCEI Microelectronic Project and will be presented in this talk.

PCB and packaging solutions for Green electronics

The usual amounts of data continue to grow exponentially. ICT currently consumes around 4% of the world's energy. Therefore one of the goals of the EU project “IPCEI” is a significant improvement the carbon footprint of digitization with the help of innovative Power semiconductors. In one example this goal will be addressed by increasing efficiency using the future generations of gallium nitride (GaN) technologies and housings for the electronics industry in Europe. In addition to circuit breakers for highly efficient energy conversion, inexpensive GaN on silicon high-frequency technologies will be developed, which accelerate the 5G expansion. Due to the large energy requirement, an efficiency improvement of only one percentage point results in a saving of approx. 10 megatons of CO2.
In this way, ICT can not only make many applications more “gree”, it can also become more “green” itself.

Power electronics for Green ICT

Power modules play a main role in traction inverter applications. They control engine speed and torque, regulating the energy flow between battery and motor. Due to the demanding electric and reliability performances requested by end costumers, semiconductor devices based on wide band gap compound are introduced in novel power modules. To support such device developments, there is the need to set a robust and accurate experimental methodology that shall be supported by numerical models. The targets are the prediction of thermal performance and the reliability forecast. In this framework, it has been proposed a dedicated flow to thermally characterize a multi-chip SiC MOSFET power module for automotive applications. Body-diode drop voltage has been selected as the temperature sensitive electric parameter to monitor the average junction temperature for thermal impedance measurements. Finite element model has been employed to predict temperature distribution due to device self-heating, referring to the previous characterization for the calibration of the numerical model. Once the thermal simulation methodology has been set, module temperature during inverter operations can be calculated, collecting temperature history profile into some loading conditions using a Rainflow-like approach. The several loading cases have been characterized by different temperature swing and cycle time. These classified data can be considered to evaluate lifetime duration due to selected failure mechanisms , supporting the definition of the most proper durability assessment for the application-relevant failure modes.

Structural characterization and simulation of a direct-cooled power module

After more than 35 years from its first conception and in the year of the recognition with the IEEE milestone, the Smart Power BCD technology is still evolving continuously and rapidly to serve at best the application requirements of new and changing markets.
As stated in the IEEE milestone for “Multiple Silicon Technologies on a Chip, 1985”, STMicrolectronics pioneered the super-integrated silicon-gate process combining Bipolar, CMOS and DMOS (BCD) transistors in single chips for power-demanding applications.
The markets currently requiring faster and higher technology evolutions are the Personal Electronics, bringing needs of wireless charging and power management, the Industrial, asking for more efficient power conversion, and the Automotive, where new challenges come from the battery management and inverter functions in Electric Vehicles and from Autonomous Driving. To meet those market requirements, the Smart Power BCD roadmap is following three key directions: digital processing capability increase (announced 40nm node with embedded non-volatile memory solutions), evolution to higher power and voltage (up to 10kV on-die galvanic isolation) and customization by application. 
We will walk along these three evolution paths, presenting their technology features and related product examples.

The Smart Power BCD evolution in the year of the IEEE milestone

AP&S wet process development on SiC wafers started in 2015 and was initiated by an inquiry from one of the worldwide leading semiconductor manufacturers in Europe. This one was faced with the task of introducing a new production line for microchips based on SiC for a new progressive automotive application. The goal to achieve efficient, high-yield and cost-effective production for SiC products thus has come in focus. One important step in this overall production process has been the reliable and cost-efficient wet processing. The joint development between the semiconductor manufacturer and AP&S, in particular the Demo Center, thus began. This journey took us from metal lift-off process to metal etching processing with endpoint detection on singlewafer application to high-volume batch processing. In this presentation both the changes in the semiconductor manufacturing processes and the solutions derived from them will be presented. Clear breakdowns of the various process data, parameters and conditions will be shown including a detailed overview of the development on SiC from 2015 to 2021.

Wet SiC Metal-Etch - From singlewafer to batch application

Silicon on Insulator is used extensively for its robustness in automotive applications.
X-FAB's BCD on SOI 180nm platform aims at high performance for HV applications and focuses on flexibility and ease of use.
It enables the integration of high voltage BCD devices for driving actuators and motors with high precision analog functions for sensor interface and signal processing. SOI in this context is relevant for its robustness such as latchup immunity and reduced high temperature leakage and also for its isolation properties.
In order to serve our foundry customers, the X-FAB 180nm BCD on SOI platform is highly modular and is fully supported by models, PDKs and design IPs.
When faced with particular operating range constraints, designers can select technology modules to optimize circuit performance for high power/high voltage interfaces.
Besides the traditional ON resistance for a given breakdown voltage, our recent development improved on the usability of the medium and high voltage options with devices ranging from 12V to over 300V. For each geometry the most suitable performance trade-off can be designed with fully characterized and modeled transistors for each voltage classe.
Our technologies are automotive qualified to grade 0 and characterized up to 175oC. We are extending the model validation up to 200oC allowing the design of sensor interfaces and drivers that will operate in a high temperature environment while allowing for dissipation and package thermal resistance.
To support the increase in digital content, non volatile memory IPs are provided either as embedded in the CMOS flow or with a dedicated SONOS module allowing denser implementation. For the SOI platform the memory IP designs are adapted for operation at hot temperature with a specific automotive friendly architecture. 


New results of Bipolar Cmos Dmos on Silicon On Insulator

High performance, low cost solid-state LiDAR systems require novel system architectures regarding sensor and readout circuits in combination with tailored illumination solutions. This talk will focus on performance trade-offs, suitable transmitting units, efficient operating modes and the integration in scalable systems. Elmos Solid State LiDAR concept heads forward to make environment detection smarter to meet upcoming requirements for new ADAS and autonomous driving.
We are presenting a scalable multi-channel laser-driver generating short high intensity pulses for direct time-of-flight measurements. Using a die stacking approach to minimize module size and parasitic inductance, peak currents of up to 50A are applied to the laser-diodes within a 1ns pulse. In addition, the laser driver has integrated functional safety diagnostics including monitoring of the average output power for eye-safe operation.
Implemented in the Elmos automotive-grade 350nm CMOS process, the laser driver is featured in our compact 905nm solid-state LiDAR system for demonstration purposes, which also includes an Elmos-designed SPAD imager.

Sub-nanosecond high-power pulsed multi-channel laser driver for time-of-flight applications

In the last 15 years, Fondazione Bruno Kessler (FBK) has developed a custom technology for single-photon avalanche diodes (SPADs) and silicon photomultipliers (SiPMs) optimized for several applications, from high-energy physics experiments to medical imaging or light detection and ranging (LiDAR). In the IPCEI framework, FBK is upgrading its microfabrication facility for the realization of 3D integrated radiation sensors. In the specific case of SiPMs, 3D integration technologies will allow to improve its capabilities by using back side illuminated (BSI) devices and Through Silicon Vias (TSV) interconnections. The BSI approach for SiPMs can be exploited to improve the current photon detection efficiency (PDE), even in the wavelength ranges far away from the visible spectrum, where typically it drops down to about 10% for the near infrared (NIR) and about 15% for vacuum ultraviolet (VUV). A first batch of BSI SiPMs for NIR detection was recently fabricated at FBK as a proof of concept. After wafer bonding and thinning, the characterization results showed an increase of the PDE of about 50% at 900 nm for BSI sensors with metal reflectors compared with the standard front side illuminated (FSI) technology. Research on the realization of the fabrication process modules optimized for near ultraviolet (NUV) and VUV BSI SiPMs is currently ongoing and will also be presented and discussed.

Characterization of Preassembly influence on Die Attach process

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Characterization of Preassembly influence on Die Attach process

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Next from ESSCIRC ESSDERC Educational Events

multi-technology wafer level integration for RFFE applications

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A 2.67 μJ Per Measurement FMCW Ultrasound Rangefinder System for the Exploration of Enclosed Environments

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COMPANY

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