France

The current electronic device scaling is reduced to 5 nm and smaller technology nodes based on EUV lithography, it is expected to reach sub-nm technology node within a decade. Along with the EUV scaling, the space of medium/upper level BEOL provides both challenges and opportunities to device research community. Rational design of device materials using atomic scaling modeling methods can contribute the accelerated development of the new technology materials based on fundamental understanding on their atomic and electronic scale properties. Using the density functional theory (DFT), atomistic kinetic Monte Carlo (KMC) and time-dependent DFT (TDDFT) simulations methods, we have been investigating the BEOL process compatible oxide semiconductors for monolithic 3 dimensional (M3D) integration of functional devices in the intermediate interconnect layers. In this tutorial, we will discuss about the multiscale modeling approaches applied to device materials modeling for n- and p-type oxide semiconductor design for BEOL applications. We will examine atomic and electronic structures of both n-type and p-type oxide semiconductors in crystalline and amorphous phases. Using the rational design approach to oxide semiconductors based on DFT calculations, we are exploring the complex oxide material parameter space and charting possible pathways to develop both p-type and n-type oxide semiconductor candidates for BEOL CMOS applications. We will discuss the design rationales of currently identified oxide semiconductor candidates (Ta2SnO6, TiSnO3 for p-type In-W-O system for n-type) and validation experiments to accelerate the focused development of BEOL oxide semiconductors with superior performance. These oxide semiconductors will provide case study examples of the materials deign method applied to electronic device materials in this tutorial. 
This work was supported by ASCENT, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

ESSCIRC ESSDERC Educational Events

Rational Design of BEOL Oxide Semiconductors for Emerging Device Applications.

p-type oxide

n-type oxide

amorphous oxide

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





tutorial

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

This talk will discuss the challenges to design and implement THz circuits in CMOS, as well as a discussion on applications. It will give an overview of the research results in this field by the MICAS group of KU Leuven, Belgium

THz circuits and applications

This presentation provides an overview of InP HBT integrated circuit technologies for mmWave and THz applications. Transistor and circuit performance will be reviewed with an emphasis on power amplifiers at mmWave and sub-THz frequencies. Heterogeneous integration techniques using wafer-scale 3D integration and device-scale microtransfer printing are also described.

InP technologies for mmW & THz wireless applications

The terahertz frequency range provides abundant bandwidth (25GHz ~ 50 GHz) to achieve ultra-high-speed wireless communication and enables data rates up to and above 100 Gbps. In this talk, I will present our early work on THz imaging and sensing with CMOS and SiGe HBTs. I will then present 6G wireless transceivers and discuss their performance and link impairments. I start with link budget considerations and address design trade-offs with respect to the used technology. The radio front-ends are manufactured in a SiGe BiCMOS 0.13um technology and operate at a tunable carrier of 220–260 GHz. The modules achieve data-rates from 20 to 100 Gbps with an EVM from 7% to 17% at a 1-meter distance using 16-QAM. I will further present our work on polarization diversity MIMO systems above 200 GHz. The MIMO link is established using a circular dual-polarization Tx and a dual-polarization Rx module. The polarization-diversity (left-handed circular polarization and right-handed circular polarization) is provided by a lens-coupled circularly polarized on-chip antenna. With this system, two independent data-streams of 55 Gb/s each were transmitted in parallel over a 1-meter line-of-sight distance, achieving an aggregated record data-rate of 110 Gbps.

SiGe HBT devices/circuits for mmW & THz wireless applications

Enabling the efficient processing of deep neural networks (DNNs) has becoming increasingly important to enable the deployment of DNNs on a wide range of platforms, for a wide range of applications. To address this need, there has been a significant amount of work in recent years on designing DNN accelerators and developing approaches for efficient DNN processing that spans the computer vision, machine learning, and hardware/systems architecture communities. Given the volume of work, it would not be feasible to cover them all in a single talk. Instead, this talk will focus on *how* to evaluate these different approaches, which include the design of DNN accelerators and DNN models. It will also highlight the key metrics that should be measured and compared and present tools that can assist in the evaluation.

How to Evaluate Efficient Deep Neural Network Approaches

As we march towards the age of “ubiquitous intelligence”, we note that AI and Machine learning are progressively moving from the Cloud to the Edge devices. The success of Edge-AI is pivoted on innovative circuits and hardware that can enable inference and limited learning, in hardware-constrained ultra-low-power (uW to mW) systems – an area of active research. In this talk, I will discuss the promises and outlook of Edge-AI and their applications in Autonomous Systems; and elaborate on some of our recent work on enabling such systems in sensor nodes and robotics. While some of these systems extend our understanding of statistical machine learning, a large class of circuits and systems are inspired by the information representation in the brain. I will talk about the design of such circuits and systems with an emphasis on the impact of mixed-signal circuits, near-memory and in-memory compute architectures, as well as algorithm-hardware co-design to realize the most energy-efficient Edge-AI ASICs for the next generation of smart and autonomous systems.

Neuro-inspired Edge-AI for Autonomous Systems

The explosive growth in the size of Artificial Intelligence (AI) models and the concomitant increase in compute intensity over the past few years is unsustainable without significant innovation across the stack. A non-von Neumann computational approach using in-memory compute is a paradigm shift that can deliver significant improvements in performance and energy efficiency for data-centric AI applications. Among the many memory options being evaluated, phase change memory (PCM) devices are attractive given their non-volatility, analog tunability & maturity of the technology. However, these devices also suffer from many non-idealities. This talk details innovations across materials, algorithms and architecture to address challenges posed by PCM device non-idealities to accelerate AI inference and training jobs.

Device, Architecture, and Algorithms Co-optimization for Scalable Analog Compute Technology

Computing-in-memory (CIM) is being widely explored to minimize powerconsumption in data movement and multiply-and-accumulate (MAC) for AI edge devices. In my talk, I will introduce several design techniques for CIM including both analog and digital approaches.

Basic introduction of SRAM based CIM including analog and digital approach

Artificial intelligence and deep neural networks (DNNs) have been successful across many practical applications, but state-of-the-art algorithms are compute-/memory-intensive. In-memory computing (IMC) has emerged as a promising technique to resolve the computation and memory access bottleneck. While many single-macro-level IMC prototypes have been demonstrated, integration and programmability challenges remain for system-level IMC accelerators. To that end, we present a programmable IMC accelerator (PIMCA) integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We will discuss architecture design and techniques employed for the PIMCA chip design, including a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of DNN layer types. The 28nm prototype chip achieves high system-level peak/average energy-efficiency of 437/289 TOPS/W.

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

When it comes to modelling materials of technological interest for microelectronics and their properties, the challenge is great, especially when considering current low-temperature processes, 3D architectures for the integration of ultra-thin, nanostructured materials with controlled performance. The continuum methods on which TCAD simulation in industrial environments typically relies are inherently unable to capture the resulting effects at these scales such as defect formation and growth mechanisms. 
In this talk, we will see how it has become necessary to implement a series of atomistic tools at different time and size scales to capture all the effects necessary for reliable process prediction. A review of atomistic methods will be proposed from the most conventional methods such as molecular dynamics and DFT to state-of-the-art methods such as going “beyond DFT” and Machine Learning potential. Examples on manufacturing process and defects characterization will be given.
Finally, one the main purpose of these studies is to help microelectronics engineers. Example of implementation of atomistic data into industrial TCAD tools will be given and discussed.

What multi-level strategy for modelling processes and defects in semiconductors at the atomic scale? Current approaches, necessary developments and new needs.

Advances in process and fabrication enable the relentless downscaling into the nanometer regime and open the way to a new era of device structures and materials. Approaching the atomic scale, individual imperfections such as point defects, which are inevitably present in bulk and interface systems, and their distributed properties start to become a decisive factor for device reliability and start to dominate the device performance. Keeping pace with the technological progress on the theoretical simulation side, hence, requires reliable approaches based on fundamental physics such as ab initio calculations. Largely driven by the beat of Moore’s law itself and the increase of computational resources, atomistic first-principles calculations are routinely used nowadays to predict structural and electronic properties. Nevertheless, understanding the underlying model together with a careful analysis of the results is essential to draw meaningful conclusions. Particularly in the field of device reliability, these advancements have enabled an improved understanding of intrinsic and extrinsic point defects in various materials such as Si/SiO2/HfO2 or SiC/SiO2 stacks. Due to the predictive power and accuracy of density-functional-based calculations characteristic defect properties such as thermodynamic and optical transition levels as well as their interaction with the surrounding can be directly connected to experimental observations. Hence, it is possible to assess how vacancy, interstitial, antisite, substitutional, and other defect types impact and perturb the device performance. Moreover, these results provide vital input for the development of modern predictive TCAD models.

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THz circuits and applications

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Bias Generation and Calibration of CMOS Charge Qubits at 3.5Kelvin in 22-nm FDSOI

Stay up to date with the latest Underline news!

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COMPANY

RESOURCES

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