Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9186799

**Abstract:**

In this study, a consistent analytical chargebased model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-numberfluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture.

ESSCIRC ESSDERC 2021

Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation

variability.

trap density

organic thin-film transistors (tfts)

mobility fluctuation

carrier-number fluctuation

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9157.pdf

**Abstract:**

As wireline transceivers continue to push for higher speeds, their power consumption becomes increasingly more critical. This paper describes methods that can reduce the power drawn by drivers and multiplexers on the transmit side and equalizers and clock and data recovery circuits on the receive side. These concepts have been incorporated in designs ranging from 40 Gb/s to 80 Gb/s in 45-nm and 28-nm process nodes.

Low-Power Techniques for Wireline Systems

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9168.pdf

**Abstract:**

This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9134.pdf

**Abstract:**

This article presents a 64-Gb/s PAM-4 TX with a proposed 4-tap hybrid feed-forward equalization (FFE). The pre-emphasis (PE) based FFE is employed to enlarge the output swing by directly stacking the distorted pulses on the main pulse. And it consumes less power than the de-emphasis (DE) based counterpart as it only boosts the desired distorted symbols. The fractionally-spaced (FS) based FFE provides compensation of signal beyond Nyquist and the post2 tap compensates for the lower-frequency signal, the combination of them realizes an accurate equalization and wide compensation range.

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9178737

**Abstract:**

A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this work. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring-oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of signal-band and also has intrinsic interferer rejection capability. A prototype ADC fabricated in 65nm CMOS is operated at an IF of 52MHz. The ADC has an SNDR of 63.1dB and 59.5dB at 1.04MHz and 4.3MHz bandwidth, respectively. The ADC consumes only 0.36mW power from a 0.9V supply and has an energy efficiency of 21fJ/step improving upon the current state-of-the-art by 3.5x.

21fJ/Step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9137304

**Abstract:**

This paper introduces a novel SAR-based algorithm that speeds up the conversion by using two digital-to-analog converters that operate in a ping-pong fashion. It has been implemented in a 4x time-interleaved analog-to-digital converter in a 16-nm FinFET technology. Each channel uses the proposed ping-pong SAR (PP-SAR) algorithm in a coarse phase followed by a comparator-based asynchronous binary search (CABS) fine phase to realize 418 MHz/channel 10-bit conversion with 51-dB SNDR at Nyquist. The total power consumption is 7.9 mW corresponding to a Walden FoM of 16 fJ/conversion-step at Nyquist.

A 1.67-GSps Ti 10-Bit Ping-Pong SAR ADC with 51-dB SNDR in 16-nm FinFET

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9183905

**Abstract:**

This letter presents a compact buffer-less 12-bit output SAR-based bridge-to-digital converter. Eliminating the sample-and-hold circuit substantially simplifies the sensor front-end by providing a high impedance input stage. The binary weighted digital-to-analog converter (DAC) is replaced with a switched-capacitor DAC which is driven by an error-feedback modulator. This alleviates mismatch issues and provides area and power savings when used with a Wheatstone bridge as a read-out. The converter has a wide input range of 830 mV making it suitable for gas sensor applications. It is realized in 65-nm CMOS, occupies 0.01 mm2 area, and consumes 6.2 μA with a 45 ms conversion time. It achieves 9.1 ENOB for a DC input and a Walden FoM of 0.65 nJ/conv-step.

A 0.01-mm2 0.83-V Input Range SAR-Based Bridge-to-Digital Converter

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9171283

**Abstract:**

This work presents a simplex and a full duplex digital communication interface that enhance the energy efficiency of chip-to-chip digital communication in low speed low power systems. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5^10-12. The simplex and full duplex interfaces achieve an energy consumption of 0.38pJ/b and 1.2pJ/b respectively. The simplex interface achieves a power reduction of 2× to 27× compared to conventional LVCMOS for data rates from 10kb/s to 50Mb/s. The full duplex interface achieves a power reduction of 5× to 11× for data rates from 100kb/s to 50Mb/s.

A 0.38pJ/B Simplex and a 1.2pJ/B Full Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9160876

**Abstract:**

The data rate-times-distance product in mm-wave dielectric waveguide (DWG) communication links is usually limited by waveguide dispersion. This letter presents the DWG\'s baseband impulse response in the context of a homodyne receiver and introduces a continuous-time linear equalizer able to minimize such dispersion. The desired transfer function is implemented with inverter-based transconductance cells. The simulation and measurement results at 10-Gbps data rate show eye-opening improvement at two distances (10 and 15 m) and carrier frequencies (140 and 160 GHz). The equalizer occupies 80 × 32 μm2 in GLOBALFOUNDRIES 22-nm FD-SOI.

A 10-Gbps Continuous-Time Linear Equalizer for mm-Wave Dielectric Waveguide Communication

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9205866

**Abstract:**

The use of new materials with advanced properties has become mandatory to meet the needs for higher electronics performance at reduced power. Topological insulators (TIs) possess highly conductive topologically protected edge states which are insensitive to scattering and thus suitable for energy-efficient highspeed devices. Here,we evaluate the subband structure in a narrow nanoribbon of 1T molybdenumdisulphide using an effective k·p Hamiltonian. Highly conductive topologically protected edge modes whose energies lie within the bulk band gap are investigated on equal footing with traditional electron and hole subbands. Due to the interaction between the edge modes at opposite sides, a small gap in their linear spectrum opens up in a narrow nanoribbon. This gap is shown to sharply increase with the perpendicular out-of-plane electric field, in contrast to the behavior in a wide nanoribbon with negligible edge modes’ interaction. This increase leads to a rapid decrease in the ballistic nanoribbon conductance and current with the electric field, which can be used for designing molybdenum disulphide nanoribbon-based current switches.

Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T\' Phase

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9210837

**Abstract:**

An analytical model for back bias capability including interface traps, quantum confinement, short channel effects is developed, which is in excellent agreement with TCAD simulations and measurements. The derived expressions facilitate the accurate assessment of interface trap impact on variability and also benefit the configuration of dynamics back bias for aging compensation, thereby fully leveraging the UTBB FDSOI technology.

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Low-Power Techniques for Wireline Systems

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Next from ESSCIRC ESSDERC 2021

Low-Power Techniques for Wireline Systems

Similar lecture

Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

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