VIDEO DOI: https://doi.org/10.48448/pxvb-rd48

technical paper

ESSCIRC ESSDERC 2021

September 14, 2021

Italy

A Real-Time Output 50-GS/s 8-Bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency

Please log in to leave a comment

Downloads

SlidesPaperTranscript English (automatic)

Next from ESSCIRC ESSDERC 2021

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, with Fast Locking and Low Power Characteristics
technical paper

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, with Fast Locking and Low Power Characteristics

ESSCIRC ESSDERC 2021

+11Hojun Yoon
Hojun Yoon and 13 other authors

14 September 2021

Similar lecture

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link
technical paper

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link

ESSCIRC ESSDERC 2021

+4Woonghee Lee
Woonghee Lee and 6 other authors

14 September 2021

Stay up to date with the latest Underline news!

Select topic of interest (you can select more than one)

PRESENTATIONS

  • All Lectures
  • For Librarians
  • Resource Center
  • Free Trial
Underline Science, Inc.
1216 Broadway, 2nd Floor, New York, NY 10001, USA

© 2023 Underline - All rights reserved