VIDEO DOI: https://doi.org/10.48448/5wr7-6k26

technical paper

ESSCIRC ESSDERC 2021

September 14, 2021

Italy

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, with Fast Locking and Low Power Characteristics

Please log in to leave a comment

Downloads

SlidesTranscript English (automatic)

Next from ESSCIRC ESSDERC 2021

An Ultra-Low Power K Band Balanced Frequency Doubler with a Novel Current-Reused Structure
technical paper

An Ultra-Low Power K Band Balanced Frequency Doubler with a Novel Current-Reused Structure

ESSCIRC ESSDERC 2021

+6Yue Gong
Yue Gong and 8 other authors

14 September 2021

Similar lecture

Fast Behavioral VerilogA Compact Model for Stochastic MTJ
technical paper

Fast Behavioral VerilogA Compact Model for Stochastic MTJ

ESSCIRC ESSDERC 2021

+2Etienne Becle
Etienne Becle and 4 other authors

14 September 2021

Stay up to date with the latest Underline news!

PRESENTATIONS

  • All Lectures
  • For Librarians
  • Resource Center
  • Free Trial
Underline Science, Inc.
1216 Broadway, 2nd Floor, New York, NY 10001, USA

© 2023 Underline - All rights reserved