Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9013.pdf

**Abstract:**

This work introduces a neuromorphic chip featuring energy-efficient transfer learning capability using a new learning rule, Delta- Spike Time Dependent Plasticity (STDP). Delta STDP enables the neuromorphic chip to leverage on its previous knowledge to learn and to solve different but related tasks at a faster rate and with a limited number (few shots) of training samples. Compared to the unsupervised on-chip learning (OCL) rules, Delta STDP offers lower learning overheads as it has ~20% lower memory utilization and is operated only on the last layer of the Spiking Neural Network (SNN). A test chip fabricated in 40nm demonstrates this on-chip learning concept using DVS gesture and MNIST datasets. It achieves an accuracy of &gt;80% for DVS gesture (using 9.8K training samples) with the total energy/learning is 5.2J at 0.5V. For MNIST, using only 2K training samples, it attains an accuracy of 97% and this learning convergence rate is &gt;10x the conventional OCLs. The total energy/learning for MNIST dataset is 8.6mJ at 0.5V. Overall, the chip consumes 2.1 pJ/SOP at 0.5V, which is 12.3x-91.4x lower compared to the existing state-of-the-art.

ESSCIRC ESSDERC 2021

A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-Chip Transfer Learning Using Delta STDP

spike-timing-dependent plasticity (stdp).

on-chip learning (ocl)

spiking neural network (snn)

transfer learning

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9013.pdf

**Abstract:**

This work introduces a neuromorphic chip featuring energy-efficient transfer learning capability using a new learning rule, Delta- Spike Time Dependent Plasticity (STDP). Delta STDP enables the neuromorphic chip to leverage on its previous knowledge to learn and to solve different but related tasks at a faster rate and with a limited number (few shots) of training samples. Compared to the unsupervised on-chip learning (OCL) rules, Delta STDP offers lower learning overheads as it has ~20% lower memory utilization and is operated only on the last layer of the Spiking Neural Network (SNN). A test chip fabricated in 40nm demonstrates this on-chip learning concept using DVS gesture and MNIST datasets. It achieves an accuracy of >80% for DVS gesture (using 9.8K training samples) with the total energy/learning is 5.2J at 0.5V. For MNIST, using only 2K training samples, it attains an accuracy of 97% and this learning convergence rate is >10x the conventional OCLs. The total energy/learning for MNIST dataset is 8.6mJ at 0.5V. Overall, the chip consumes 2.1 pJ/SOP at 0.5V, which is 12.3x-91.4x lower compared to the existing state-of-the-art.

technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9058.pdf

**Abstract:**

This paper presents circuit monitoring, reviewing different classes of silicon monitoring solutions, the specificity of each class and where they best fit in the life-cycle of circuit design. Circuit monitoring for Silicon versus Computer-Aided- Design (CAD) calibration. In-Die test and In-Field compensation using Adaptative Voltage Scaling (AVS) or Adaptative Body-Bias (ABB) or both are discussed. Illustrations of Silicon measurement or CAD simulation analysis from 40nm CMOS general purpose, 28nm FD-SOI automotive are exposed.

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS Technologies

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9344.pdf

**Abstract:**

InGaAs is an attractive material for high-speed, high-frequency electronics and ultra-low-noise applications. This paper discusses a number of interesting device physics in nanoscale InGaAs FinFETs of relevance to the development of electronics based on other material systems: excess off-state current due to band-to-band tunneling and a parasitic lateral bipolar transistor effect, ballistic mobility and injection velocity, as well as a new technique to extract the charge-control relationship in the presence of severe gate oxide trapping.

Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9015.pdf

**Abstract:**

The subject of the paper is substrate capacitance modeling for MOSFET-based RF switches on high-ohmic silicon substrates. Microstrip line computational models are applied for calculating the capacitance. It is proposed to use inverted microstrip line model for the flip-chip IC mounting configuration. The model-to-hardware correlation has been demonstrated on a prototype switch IC fabricated in a dedicated 130nm bulk- CMOS technology. The calculated switch RF breakdown voltages (serving as an indicator for the substrate capacitance) of 56V and 54.8V was measured to be 55.4V and 51.4V for the wire-bonded and flip-chip ICs respectively.

Model of Substrate Capacitance of MOSFET RF Switch Inspired by Inverted Microstrip Line

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9207.pdf

**Abstract:**

With rising demand for higher frequency system-on-chip MEMS, accuracy in the modelling and design phase becomes increasingly important. The impact of mechanical anisotropic layers on the acoustic band gap formation in a CMOS back-end-of-line Bragg mirror is studied by analytic and finite element approaches. In particular the influence of anisotropic monocrystalline copper sheets, with varying crystal orientations, is investigated for monolithic high-Q MEMS resonator confinement. It is shown that for a mechanical FinFET resonator in the front-end-of-line multiple resonant frequencies can coexist on the same wafer, depending on the spatial extents of the device. All of which need to be accommodated by a broadband mechanical band gap in the back-end-of-line which is demonstrated for different anisotropic copper crystal orientations.

Mechanical Band Gap Formation in Anisotropic CMOS Back-End-of-Line Stacks for Monolithic High-Q MEMS Resonator Confinement

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9276.pdf

**Abstract:**

We present a study based on numerical simulations and comparative analysis of recent experimental data concerning the operation and design of FeFETs. Our results show that a proper consideration of charge trapping in the ferroelectric-dielectric stack is indispensable to reconcile simulations with experiments, and to attain the desired hysteretic behavior of the current-voltage characteristics. Then we analyze a few design options for polysilicon channel FeFETs and, in particular, we study the influence of the channel thickness and doping concentration on the memory window, and on the ratio between the polarization dependent, high and low resistance state.

Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9170.pdf

**Abstract:**

A compact analytical model is reported capturing the effects of Coulomb Blockade and charge quantization on the drain current characteristics of a MOSFET-based semiconductor quantum dot at cryogenic temperatures. It is implemented as a Verilog-A add-on to the foundry-provided MOSFET model to facilitate potential integration in any design kit and allow for simulation of quantum processors that integrate qubits and control electronics on the same die. The model was verified in the 6-50 K temperature range on the measured I-V characteristics of a nanoscale p-MOSFET fabricated in production 22nm FDSOI CMOS technology.

Compact Modelling of 22nm FDSOI CMOS Semiconductor Quantum Dot Cryogenic I-V Characteristics

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9050.pdf

**Abstract:**

In this paper, we propose a fully integrated area-efficient bias generation system using a single input reference for a 2D quantum core structure comprising quantum dot arrays. The arrangement of biases initializes the quantum structure before a sophisticated quantum experiment can commence. The circuit area is 0.011mm^2 and the power consumption is 220uW at 3.5K with a 0.8V supply in a 22nm FD-SOI process. The proposed scheme can be readily extended to more complex quantum structures.

Bias Generation and Calibration of CMOS Charge Qubits at 3.5Kelvin in 22-nm FDSOI

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9302.pdf

**Abstract:**

A novel coherent optical link is proposed to serve as the interconnection technology between the room temperature and cryogenic temperature environment for quantum computing and high-performance superconducting computing. The trade-off on the energy efficiency of this link is discussed. A prototype optical transmitter is fabricated in the 45RFSOI CMOS process and characterized at the cryogenic temperature. Measurement results show that this optical transmitter is able to be directly driven by superconducting electronics with millivolt-level voltage swing, and the new link has five times better energy efficiency than the traditional intensity modulation, direct-detection link.

Electronic-Photonic Cryogenic Egress Link

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9068.pdf

**Abstract:**

Digital PLLs are nowadays recognized as a viable approach for the design of high-performance frequency synthesizers in scaled CMOS technologies. Latest implementations allow achieving at low power both state-of-the-art rms jitter, between 50fs and 100fs, and highly linear fast frequency modulation capability, thus enabling both high-efficiency communications systems and radar applications in CMOS. This paper will briefly trace the path from the (re-)discover of this approach to the more recent solutions, discussing the main characteristics of key building blocks and their limitations such as the non-linearities, and the noise, that still calls for a sound knowledge of analog design techniques.

Digital PLLs: the Modern Timing Reference for Radar and Communication Systems

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9322.pdf

**Abstract:**

We examine the potential design and performance of 100-300 GHz wireless communications systems, examine the required transistors performance, and describe our present efforts to develop InP bipolar and field-effect transistors to serve in the transmitters and receivers of such systems .

A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-Chip Transfer Learning Using Delta STDP

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A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-Chip Transfer Learning Using Delta STDP

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Next from ESSCIRC ESSDERC 2021

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS Technologies

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