Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9143.pdf

**Abstract:**

IoT end-nodes require extreme performance andenergy efficiency coupled with high flexibility to deal with theincreasing computational requirements and variety of mod-ern near-sensor data analytics applications. Low-Bitwidth andMixed-Precision arithmetic is emerging as a trend to addressthe near-sensor analytics challenge in several fields such aslinear algebra, Deep Neural Networks (DNN) inference, andon-line learning. We present Dustin, a fully programmableMultiple Instruction Multiple Data (MIMD) cluster integrating16 RISC-V cores featuring 2b-to-32b bit-precision instruction setarchitecture (ISA) extensions enabling fine-grain tunable mixed-precision computation. The cluster can be dynamically configuredin Vector Lockstep Execution Mode (VLEM), turning off all IFstages except one, reducing power consumption by up to 38%with no performance degradation. The cluster, implemented in65nm CMOS technology, achieves a peak performance of 58GOPS and a peak efficiency of 1.15 TOPS/W.

ESSCIRC ESSDERC 2021

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

energy efficient simd computing

lockstep execution

trans-precision computing

ultra-low-power digital design

risc-v

simd computing

tiny ml

ml acceleration

parallel computing

embedded systems

quantized neural networks

machine learning

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9194762

**Abstract:**

In this paper a stitched array of 768x64 pixels for X-ray dental imaging is presented. The sensor architecture allows to increase the frame rate up to 900 fps thanks to a pipeline approach that minimizes the deadtime between consecutive frames. A column-based ADC converts pixel values in digital form while an external FPGA performs the operation of TDI accumulation, thus increasing the SNR. Internal programmable gain allows to achieve a maximum sensitivity of 2.6 LSB/nGy and, at the same time, to extend the dynamic range of the sensor in case of high intensity. The final system consists of two sensors each one having a size of 74.5x9 mm, assembled in a PCB and coupled with a high sensitive columnar thallium-doped cesium iodide (CsI(Tl)) scintillator for X-ray conversion. The sensor, fabricated in a standard CMOS 0.15um technology with stitching approach, shows a pixel size of 97 um

Luximos: a 768x64 900-fps Tileable Pipelined X-Ray CMOS Image Sensor for Dental Imaging with 2.6 LSB/nGy Sensitivity

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9174634

**Abstract:**

This paper presents the design and experimental characterization of an ultrasound rangefinder system. A new distance measurement method is proposed for determining the relative position among sensor nodes that are operated in a collision and multipath rich environment, while needing no common time reference between them. A 65nm CMOS technology has been used to build the sensor nodes, which comprise an on-chip receiver and transmitter. The proposed rangefinder system is characterized up to 1m in air and has a range resolution of 6.5mm, while dissipating 2.67 μJ per measurement.

A 2.67 μJ Per Measurement FMCW Ultrasound Rangefinder System for the Exploration of Enclosed Environments

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9212567

**Abstract:**

To pave the way for system-on-chip MEMS confinement up to 50 GHz, the mechanical properties of a CMOS back-end-of-line (BEOL) are studied by analytic and finite element approaches. In particular, the two main directions of vertical and horizontal wave propagation are investigated. With respect to the symmetry of the BEOL, the movement through the nonperiodic horizontal layers is described by the Rayleigh-Lamb equation. It is shown that our finite element method (FEM) approach, preventing Brillouin zone folding, can be employed in simulations of these structures, since the results are in excellent accordance to the corresponding analytical solutions. The vertical propagation through the periodic stack on the other hand is subject to phononic crystal effects resulting in Bragg-like band gaps (BGs) for either a certain or every polarization. Factoring in both types of propagation, it is demonstrated by our FEM simulations how these BGs can be tailored to specific values through variations in the BEOL layers to improve the quality factor of monolithically integrated MEMS devices.

Polarization Independent Band Gaps in CMOS Back-End-of-Line for Monolithic High-Q MEMS Resonator Confinement

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9212568

**Abstract:**

Previous work has shown that optomechanical resonators are particularly well suited to the design of ultrasensitive mass sensors. They present an extremely low noise level, very high optical quality factor (Q > 10^5), excellent integration density and can resonate both in a gaseous and liquid environment. In order to reduce the long measurement time due to their small particle-capture area, several such resonators must be integrated onto the same chip. However, bulky laboratory equipment currently used to read a single optomechanical resonator cannot be practically scaled up to a large array of transducers. It is then required to design and eventually integrate a read-out interface that can process tens to thousands of resonators. To ease the design of such a circuit, this article presents a compact analytical model of an electrostatically actuated optomechanical resonator implemented in Verilog A. The proposed model includes both the optical and mechanical behaviors, as well as optomechanical coupling and thermooptical effect. It was simulated in the Cadence Virtuoso environment and is consistent with the measured results.

Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog a

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9174.pdf

**Abstract:**

We present the first fully-integrated universal Maximum Likelihood decoder in 40 nm CMOS using the Guessing Random Additive Noise Decoding (GRAND) algorithm for low-power wireless applications. The 0.83 mm^2 multi-code multi-rate universal decoder can efficiently decode any code of length up to 128 bits with 1 μs latency at 68 MHz. Dynamic clock gating leveraging noise statistics reduces the average power dissipation to 3.75 mW at 1.1 V or 30.6 pJ/decoded bit with a throughput of 122.6 Mb/s. Universal decoding reduces hardware footprint, and the design allows seamless swapping between codebooks with no downtime, enabling use by multiple applications without switch-over.

Multi-Code Multi-Rate Universal Maximum Likelihood Decoder Using GRAND

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9185.pdf

**Abstract:**

All-digital millimeter-wave massive multi-user MIMO receivers enable extreme data-rates but require high power consumption. To reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband processing to the instantaneous communication scenario. The scalable 32-antenna, 65nm CMOS receiver occupies a total area of 8mm2 and integrates ADCs with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98Gb/s while being at least 2x more energy-efficient than state-of-the-art designs.

A Resolution-Adaptive 8mm² 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9034.pdf

**Abstract:**

We present a hardware accelerator, fabricated in180 nm CMOS, for baseband timing of BLE mesh networks. The timing circuitry augments the BLE physical layer with a new command that enables scalable synchronization and aggressive duty-cycling of mesh nodes for low-power P2P communication. The custom ASIC contains a digital correlator which enables low-latency detection of a BPSK synchronization packet, or syncword. The detected syncword advances the phase of a nonlinear pulse-coupled oscillator, which drives the network to a synchronized state. The accelerator interfaces with the AD9364 software-defined radio via a ZedBoard to make a fully functional node. Duty-cycled multi-hop communication is demonstrated with total power consumption per radio node of less than 1mW while communicating 64-bit 10 MSPS packets

Scalable Digital Synchronizer for Enabling Hardware-Level BLE Mesh Networks Under 1mW

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9288.pdf

**Abstract:**

A new standard cell topology, Dual-Input Pseudo-CMOS (DIPC), for dual-gate Indium-Gallium-Zinc-Oxide (IGZO) thin-film transistor (TFT) technology on flexible substrates is presented. The proposed logic topology is compared with the conventional Pseudo-CMOS in terms of robustness (noise margin), speed performance, power consumption and area usage. This work shows that the back-gate of a TFT can be used as a separate parallel transistor reducing the number of devices in logic gates without compromising the speed and the power. Two 32-bit code generators for RFID transponders with both libraries have been designed and fabricated using n-type only TFTs with a channel length of 5 micrometers. The proposed topology allowed to reduce the number of TFTs by 24% and the chip consumes only 2.2 microwatt of power at 4 kHz clock frequency and 1 V of supply voltage. This work also forecasts that the number of TFTs can be reduced strongly by using the proposed DIPC topology for complex designs such as arithmetic logic units and microprocessors.

Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9165.pdf

**Abstract:**

This work presents a 16mm2 heterogeneous RISC-V SoC composed of a high-performance out-of-order core, energy-efficient in-order core, data-parallel vector accelerator, and systolic array DNN accelerator in low-power Intel 22FFL for general-purpose compute, DNN, and vector workloads. The heterogeneous RISC-V SoC is composed of fully open-sourced components, including a second-generation Berkeley Out-of-Order Machine (BOOM) with a non-speculative mode attached to a Hwacha vector accelerator, a Rocket in-order core attached to a Gemmini systolic array DNN accelerator, as well as a 1MiB L2 cache and off-chip I/Os. Combined, the variety of heterogeneous compute allows for wide programmability while providing up to a 286x improvement in MOPS/W or 282x MOPS improvement over the RISC-V in-order core.

A 16mm² 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9156.pdf

**Abstract:**

We present Thestral, a 10-core RISC-V chip for energy-proportional parallel computing manufactured in 22nm FD-SOI technology, featuring a control core and a nine-core compute cluster, with specialized units for floating-point (FPU) and integer (IPU) extensions. Each FPU, IPU, and the whole cluster can be independently power-gated with a sub-10 ns power-up sequence, allowing fine-tuning of leakage vs. dynamic power ratio. We achieve up to 42% measured power savings in a low-power, near-threshold operating point (@350 MHz, 0.6V, 25 °C). In a high-performance operating point (@850 MHz, 0.9V, 75 °C), a many-core Thestral may save up to 41% power during memory-bound application phases.

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

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A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

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Next from ESSCIRC ESSDERC 2021

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Machine Learning Prediction of Defect Structures in Amorphous Silicon Dioxide

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