Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9111.pdf

**Abstract:**

Current millimetre-wave (mmW) 5G NR standard supports multiple bands at 24.5/28/37/39/43/47GHz for communications. To cover several bands of the 5G NR and reaching lower end of unlicensed 60GHz band for 802.11ad, This work presents a wideband phased array front-end with LNA and two VGAs for scalar-only weighting function, and a wideband combining network of each signal weight in mmW domain for beamforming. In this work, two array elements are combined in two cascaded stages for extremely wideband operation. Combined load resonances are distributed and adjusted appropriately in each of the combining stages to achieve a flat response over the band of 38.5-60.5GHz. A single array path achieves rms gain of 8.5-12.5dB, noise figure of 6.2-8.1dB, and IP1dB of -33 to -26dBm. The measurements show ~ 6dB of array gain when the two phased array elements are combined in phase with +0.6dB to -0.4dB maximum gain error in the mmW VGAs. The prototype is implemented using 28nm CMOS.

ESSCIRC ESSDERC 2021

A 38.5-to-60.5 GHz LNA with Wideband Combiner Supporting Cartesian Beamforming Architecture

wideband front-end

cartesian beamforming architecture

wideband mmw-combining

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9187832

**Abstract:**

An area-efficient inductive coupling interface for a 3-D-stacked high-bandwidth memory is presented. A test chip was fabricated in a 40-nm CMOS technology and 1.5-Gb/s 2.2-pJ/bit communication using a 0.23-V NMOS transmitter and 7-µm multi-layer coils was experimentally confirmed. The low-voltage transmitter reduces power dissipation by 55% in measurement. The proposed 7-µm multi-layer coils improve their mutual inductance by a factor of 4.5 compared with conventional single-layer ones. Using this interface, a memory module consisting of eight 8-µm-thick memory dies and a base die in a 40-nm CMOS process is extrapolated to achieve a 2.3-Tbps/mm2 area efficiency and 6.1-pJ/bit energy efficiency.

Area-Efficient Multi-Hop Inductive Coupling Interface for 3D-Stacked Memory with 0.23-V Transmitter and Sub-10-μm Coil Design

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9158520

**Abstract:**

We proposed 3D-based redundancy scheme for stacked DRAM systems, which enables high productivity with wafer-on-wafer (WOW) technology. Vertically replaceable block scheme, and redundantly added wafer stack(s) are the keys of this technique. Memory bank replacement of vertical combinations is taken into consideration. Random defect yield loss, which is a fundamental barrier for both of the WOW technology and the leading-edge technologies, is dealt with in this study. Evaluation of many layers stacking capability leads to the result, that 3D redundancy technique is applicable even for devices with many layers of stacking. Therefore, this technique makes the WOW technology, as another system scaling enabler.

Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9154.pdf

**Abstract:**

We demonstrate the first MRAM-based IMC macro, implemented in an advanced-node 22nm FD-SOI technology from GF and achieving high row parallelism, for maximizing IMC gains. Our implementation is enabled by high-sensitivity pitch-matched readout circuits, addressing non-idealities using both circuit and software techniques. We present basic operation and neural-network (NN) CIFAR-10 classification, leveraging a generalized training algorithm and achieving 5.1 TOPS/W and 758 GOPS/mm2.

A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9056.pdf

**Abstract:**

RRAM-based compute-in-memory (CIM) has shown great potentials for deep neural network inference. Prior works generally used off-chip write-verify for tightening resistance distributions and off-chip ADC references to fine-tune partial sum quantization, which may be unsuitable for practical applications. This work presents an RRAM-CIM macro that features 1) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift, and 2) on-chip ADC reference generation that provides column-wise tunability to mitigate ADC offsets to guarantee CIFAR-10 accuracy of >90%. The design is taped-out in TSMC N40 RRAM process, and achieves 36.4TOPS/W on VGG-8 network.

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9196.pdf

**Abstract:**

By alleviating the multiply operation with simple XNOR, Binary Neural Networks seem an appealing solution to overcome the von Neumann bottleneck. In this context, we demonstrate experimentally the robustness of XNOR operation, in memory, based on resistive bridge (2T2R cell), with complementary coding of weights and input neuronal activations. Based on these measurements, we validate, through an extensive set of Monte Carlo simulations, that this approach is suitable for large neurons with very low error rate. Based on circuit results, Neural network simulations shows a very limited accuracy degradation on the MNIST task (0.07%) and CIFAR-10 task (0.35%).

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9195.pdf

**Abstract:**

The persistent and switchable polarization of ferroelectric materials based on HfO2-based ferroelectric compounds, compatible with large-scale integration, are attractive synaptic elements for neuromorphic computing. To achieve a record current density of 0.01 A/cm2 (at a read voltage of 80 mV) as well as ideal memristive behavior (linear current-voltage relation and analog resistive switching), devices based on an ultra-thin (2.7 nm thick), polycrystalline HfZrO4 ferroelectric layer are fabricated by Atomic Layer Deposition. The use of a semiconducting oxide interlayer (WOx<3) at one of the interfaces, induces an asymmetric energy profile upon ferroelectric polarization reversal and thus the long-term potentiation / depression (conductance increase / decrease) of interest. Moreover, it favors the stable retention of both the low and the high resistive states. Thanks to the low operating voltage (<3.5 V), programming requires less than 10-12 J for 20 ns long pulses. Remarkably, the memristors show no wake-up or fatigue effect.

High-Conductance, Ohmic-Like HfZrO4 Ferroelectric Memristor

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9088.pdf

**Abstract:**

The development of robust artificial sensory systems that will be able to detect, memorize and respond to external stimuli is attracting a considerable amount of interest over the last years towards emulating artificial skin properties. Along these lines, we report here a sensory system that has the ability to detect various strain loads with excellent sensitivity and at the same time respond and store the applied stimuli. In order to attain this goal, we used a bipolar switching memory device made on poly-ethylene naphthalate (PEN) substrate and Pt nanoparticles (NPs)-based sensor on poly-dimethylsiloxane (PDMS). The memristor operates only under strain conditions and retains the induced resistance changes even when the applied stain gauge is removed with <20% resistance attenuation. Additionally, paired-pulse facilitation (PPF) and long-term plasticity (LTP) effects are demonstrated indicating the potential perspective of our approach to performing neuromorphic computations with low power consumption.

Emulating Artificial Mechanoreceptor Functionalities from SiO2-Based Memristor and PDMS Stretchable Sensor for Artificial Skin Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9063.pdf

**Abstract:**

This paper presents a multi-band direct-conversion receiver with frequency-translated feedback. The forward path includes a low-noise transconductance amplifier followed by four-phase passive mixers which drive baseband amplifiers, and the feedback path employs tunable resistor banks attached to additional four-phase passive mixers, allowing tunable frequency-selective input matching. The receiver operates from 4-31 GHz exhibiting greater than 25 dB gain through 22 GHz and greater than 17 dB gain through 31 GHz. Noise figure is 5.2 to 9.8 dB, rising with frequency; input-referred 1-dB compression point is -17 dBm; and in-band IIP3 is -6.6 dBm. Out-of-band 1-dB blocker compression is greater than -12 dBm. The receiver core consumes 91 mW, whereas an integrated 2:1 frequency divider and pass-gate buffer for generating non-overlapping four-phase clocks consumes an additional 87-227~mW from 4-31 GHz, respectively.

A 4-31GHz Direct-Conversion Receiver Employing Frequency-Translated Feedback

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9274.pdf

**Abstract:**

We present a tunable LNA for software defined radio based on a compact, tunable transmission line (CTTL) element. The CTTL acts as a passive, widely tunable LC resonance in a cascoded, common source LNA to implement an instantaneously narrowband, multi-octave tunable LNA. The resulting circuit, fabricated in 65nm CMOS, is tunable from 3.5- 20GHz, and consumes 12 mW with gain >12dB, ≥−9.6dBV in-band P1dB, and OOB B1dB up to 31dB higher than the in-band B1dB due to the CTTL-tuned LC filtering. The CTTL-tuned LNA represents a more blocker-tolerant approach to achieving high frequency, software-defined LNAs without significant com- promises in other LNA performance metrics.

A Low Power, 3.5-20GHz Tunable LNA with Out-of-Band Blocker Filtering Based on Compact, Tunable Transmission Line (CTTL) Resonators in 65nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9135.pdf

**Abstract:**

This paper reports a 45-GHz low-noise amplifier (LNA) covering 22.2% –1-dB fractional bandwidth (BW). The transformer-based magnetically-coupling resonators with the gain response staggering techniques are exploited to improve its BW efficiency and gain flatness. Moreover, the 3-coil transformer-based gm-boosting common-gate scheme is utilized as the input matching network to improve the noise figure. The prototype fabricated in a 65-nm CMOS process demonstrates a maximum gain of 30.5 dB and minimum noise figure of 4.1 dB, the –3-dB BW is 15 GHz, and the –1-dB BW is 10 GHz fully covering the band range for IEEE 802.11aj. The LNA consumes 63.6-mW power with a 1.2-V supply and occupies an area of 0.47 mm × 1.00 mm.

A 38.5-to-60.5 GHz LNA with Wideband Combiner Supporting Cartesian Beamforming Architecture

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