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IEEE ISSCC Innovation

February 13, 2021

United States

Presentation digest / paper:

https://submissions.mirasmart.com/verify/ISSCC2021/Underline/Innovations/Digest/D07_06.pdf

Please vote for this presentation on the following link:

http://submissions.mirasmart.com/ISSCC2021/Rating/RegularSession.aspx?esi=65aJAiQcF

Abstract:

In Paper 7.6, Sony presents a 50.1Mpixel, 4.16µm-pitch, back-illuminated stacked CIS with a pipelined column-parallel kT/C noise-cancelling sample-and-hold circuit and a 14b delta-sigma ADC achieving 1.18e-rms random noise at 250fps. The design splits the pixel signal line to lower the wiring load and increase the operation speed.

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