Memory window(MW) closure, read delay, and gate leakage are key reliability challenges in ferroelectric field-effect transistors(FEFETs).We present a correlative study, revealing how trap generation and polarization switching during cycling affect these mechanisms.MW degradation and reduced MW recovery with read delay are linked to slow electron traps formed under bipolar stress.Gate leakage measurements and Ginestra™ simulations show these traps are primarily near the interfacial layer(IL).Minimizing slow traps in the IL is critical for improving FEFET reliability.