keywords:
non-voltile memory
transistor
ferroelectric
We propose novel Ferroelectric (FE) Field-Effect Transistor (FeFET) configuration designed to expand the memory window (MW) and enhance retention via two strategies. Our first approach is insertion of charge trap layer (CTL) between gate interlayer (G.IL) and FE layer, providing favorable trapped charge with deep trap levels. The second approach is utilization of high spontaneous polarization and low remanent polarization AFE, which results in enhanced retention by maximizing portion of QN and minimizing depolarization field.
