STT-MRAM materials and technology have recently matured to the point of moving from “lab to fab” for 28nm-22nm node standalone and eNVM applications. Prior work has mostly placed MTJ devices above M2 or even higher in the BEOL stack, depending on the application and integration constraints [1-4]. However, optimizing MRAM for mobile or last-level cache applications requires significant improvements in write speed, write current, endurance, and density of both the MRAM cell in addition to the CMOS [5]. In this work, we present the first Embedded Spin-Transfer-Torque MRAM (eMRAM) technology in a 14 nm CMOS node. Using a 2 Mb eMRAM macro, we achieve an integration at tight MTJ pitch (0.0273 um2 cell size), which is aggressively placed between M1 and M2. We demonstrate read and write functionality, including write performance down to 4 ns, and show that the eMRAM process module can be added while obeying the existing CMOS logic BEOL design rules and reliability requirements. Several unit process innovations enabled this integration, including a novel sub-lithographic microstud (μ-stud) bottom electrode (BEL), fine profile control of the MTJ patterning and dielectric films, optimized BEL/MTJ metallization, and optimized post-MTJ low-k planarization across array and logic areas. The result preserves the minimum 3 added mask levels (2 critical for μ-stud and MTJ; 1 non-critical for MTJ alignment marks), without mask-adders for low-k planarization or top electrode (TEL). A shrink patterning process ensures that the μ-stud top CD is always smaller than the MTJ bottom CD, for MTJ sizes down to below 35 nm. This minimizes shunting by eliminating the BEL resputtering onto the MTJ sidewalls during patterning, and increases etch budget. The μ-stud BEL module re-uses current manufacturing processes. Figure 1 shows a TEM cross section of 41nm MTJ devices with a sub-lithographic μ-stud underneath. The alternating MTJ pitch presented a challenge for IBE overetch/cleanup without excessive dielectric gouge. Additional tests were completed showing good device scalability to 35nm, with magnetic property degradation at smaller sizes due to edge damage that could be improved with further etch optimization. Cache applications require writing at high speed with high cycling endurance, but data retention performance can be relaxed (e.g. using ECC and data scrubbing). Figure 2 shows the eMRAM write performance. The array was written to the 1 state, then to the 0 state, versus write pulse voltage and width. The curves show the write voltage for passing median bits vs. write pulse width, from 4 ns - 20 ns. Stack B incorporated materials optimizations to reduce write voltage and time for suitability towards the last level cache. We performed a series of retention bakes at 85°C on arrays of target and smaller sized devices, demonstrating projected fail rates well below 1 ppm for retention times of ≤1 min. at nominal 43 nm CD. Results also include endurance cycling tests on 128 kb arrays up to 5x106 cycles, and single MTJs up to 1010 cycles. No dielectric breakdown or resistance drift was observed in either case. Finally, an early BEOL reliability assessment of electromigration and time-dependent dielectric breakdown supports our eMRAM embeddability for high-performance logic applications.

**References:**

[1] S. Aggarwal, et al., IEEE IEDM, San Francisco, pp. 2.1.1-2.1.4, 2019. [2] K. Lee, et al., IEEE IEDM, San Francisco, pp. 2.1.1-2.1.4, 2019. [3] W. J. Gallagher, et al., Symposium on VLSI Technology, Kyoto, pp. T190-T191, 2019. [4] J. G. Alzate et al., IEEE IEDM, San Francisco, pp. 2.4.1-2.4.4, 2019. [5] S. Sakhare et al., IEEE IEDM, San Francisco, pp. 18.3.1-18.3.4.2018.

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/4ca2fc66e4cfa0a482eef090a40fd8bc.jpg)
Figure 1: TEM cross section of 41nm MTJ devices inserted between the 14nm node M1 and M2 levels. The mstud enabled sufficient overetch & cleanup during MTJ patterning.

![](https://assets.underline.io/uploads/markdown_image/1/image/005730caa67f8294cda72db1f933d05e.jpg)
Figure 2: Passing median bit write voltage vs write pulse width for both W0 and W1 operation. Stack B improvements to the free layer enabled higher speed 4ns switching.

Michael Rizzolo

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