This paper studies on NBTI starting with 100 ns in DRAM for the first time. Ultra-fast e-traps were isolated by advanced CP. Distinct types of slow traps were separated using DMP. Considering NMP theory, we precisely obtained spatial and energy distribution of various traps and, through comparison with ab-initio calculations, revealed that these traps originate from nitrogen substitution, oxygen vacancies, and nitrogen interstitial. The results contribute to understanding of the reliability of DRAM.

DRAM Technology under Negative Bias Temperature Instability (NBTI) : from Characterization to Physical Origin Identification

This paper leverages efficient defect separation technology to model and characterize PBTI in nFinFETs with advanced nodes. Two types of traps are identified, including Type-Be1 and Type-Be2, which can be well described by three-state NMP theory. Type-Be2 is in the IL layer and may originate from Vo or HB in SiO2. Type-Be1 is in the HK layer but its origin is still unclear. Finally, the impact of PBTI on circuit performance is also assessed.

Investigation of Positive Bias Temperature Instability in advanced FinFET nodes

This paper proposes an automated RTN analysis including the detection and identification of number of traps based on non-Gaussian nature of RTN. In addition, we improve the efficiency of HMM algorithm through an adaptive model, achieving over 10 times faster performance compared to conventional method. Finally, we incorporate the impact of RTN into the reliability model by utilizing the OMI. This integration allows for circuit simulations in SPICE, facilitating the design of robust circuits.

A New Method of Automatic Extraction of RTN and OMI-friendly implementation

We reveal that negative body bias stress significantly enhances carrier energy near the bottom of the Fin, consequently exacerbating HCD in nFinFET. Furthermore, with the increase in negative body bias stress, the proportion of traps at the bottom of the Fin gradually increases, consequently weakening the body bias modulation effect. We introduce a novel characterization technique that employs body bias modulation of Vth to differentiate the distribution of traps within the vertical Fin direction.

Investigation of Interplays between Body Biasing and Hot Carrier Degradation (HCD) in Advanced NMOS FinFETs

In this paper,we have developed a new convolution-based methodology to estimate the dynamic time-evolutionary degradation of pixel circuits in display applications. For the first time, we have enabled real-time observation of the threshold voltage changes over time in key driving TFTs under different bias conditions in transient simulations of pixel circuits. Additionally, we introduce an optimized 9T2C pixel compensation circuit,which is an approximately 50% improvement over the 0.73μA observed in the 7T1C configuration.

Convolution-Based Vth Shift Prediction and the New 9T2C Pixel Circuit in LTPS TFT AMOLED

We investigated the RowPress (RP) effect for sub-20 nm DRAM. Single- and double-sided RP are compared with row hammer (RH). Distinct RP leakage mechanisms are identified, illuminating its different cell vulnerability in contrast to RH. AWL-induced RP results in 0 failure, whereas PWL-induced RP leads to 1 failure, demonstrating different bit-flip directionality from RH. Mechanisms behind the differences in the dependences on temperature and access pattern between RH and RP are analyzed.

Understanding the Physical Mechanism of RowPress at the Device-Level in Sub-20 nm DRAM

This work proposes a methodology to predict thermal profiles in gate-all-around nanosheet circuits, considering thermal coupling in devices and interconnects. It establishes a cross-layer thermal resistance network model, validated against finite element simulation. This model predicts thermal effects on circuit performance and reliability. Neglecting these thermal couplings introduces significant errors. This work aids thermal-aware circuit design beyond the 3nm node.

A Thermal Profile Prediction Methodology for Nanosheet Circuits Featuring Cross-Layer Thermal Coupling Effect

Accurate identification of protein nucleic-acid-binding residues poses a significant challenge with important implications for various biological processes and drug design. Many typical computational methods for protein analysis rely on a single model that could ignore either the semantic context of the protein or the global 3D geometric information. Consequently, these approaches may result in incomplete or inaccurate protein analysis. To address the above issue, in this paper, we present CrossBind, a novel collaborative cross-modal approach for identifying binding residues by exploiting both protein geometric structure and its sequence prior knowledge extracted from a large-scale protein language model. Specifically, our multi-modal approach leverages a contrastive learning technique and atom-wise attention to capture the positional relationships between atoms and residues, thereby incorporating fine-grained local geometric knowledge, for better binding residue prediction. Extensive experimental results demonstrate that our approach outperforms the next best state-of-the-art methods, GraphSite and GraphBind, on DNA and RNA datasets by 10.8/17.3% in terms of the harmonic mean of precision and recall (F1-Score) and 11.9/24.8% in Matthews correlation coefficient (MCC), respectively.

CrossBind: Collaborative Cross-Modal Identification of Protein Nucleic-Acid-Binding Residues

Assessment of transistor degradation in analog circuits during aging effect is challenging due to wide spread of operating points. This paper presents our proposed characterization approaches of full ID-VG
degradation for large and nanoscale devices respectively. Threshold voltage shift and mobility degradation in large devices can be extracted simultaneously with fast measurement speed (tm=3us). Based on this, full ID-VG
degradation can be assessed intuitively. Impacts of individual defects on full ID-VG degradation in nanoscale devices are characterized with the proposed approach with high resolution. Thus this paper provides a helpful solution to the characterization of device degradation in analog circuits.

Towards the Characterization of Full ID-VG Degradation in Transistors for Future Analog Applications

In advanced DRAM technology, buried-channel-array transistor (BCAT) will generate additional leakage during long-term read/write operations, leading to retention time reduction. In this work, we designed the accelerated aging test in wafer level and proposed a model for the long-term retention time prediction. By adding into conventional retention time simulation flow, the data of retention time at different operation time can be predicted. It was found that the aging can degrade retention time tail around 13% in 10 years. This work is thus helpful to the refresh scheme development considering aging effect.

New Insight into the Aging Induced Retention Time Degradation of Advanced DRAM Technologies

Periphery pFETs fabricated with the sub-20nm technology are investigated under hot carrier stress conditions when the gate voltage (|Vg|) is lower than the drain voltage (|Vd|). Two types of defects are identified: the donor-like interface trap generation causes the positive charge formation while the electron trapping in oxide traps leads to the negative charge accumulation. The corresponding energy and spatial locations are identified by analyzing the defect-induced mobility degradation and the recovery characteristic. Finally, a defect-based model is proposed for both the threshold voltage shift and the mobility degradation, which allows the prediction of the full IV after aging. This work paves a new avenue to develop accurate reliability model of periphery pFETs, a prerequisite for future device/circuit co-optimization in DRAM peripheral circuits.

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies

9B (Memory Reliability)

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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To access the site please register [**here**](https://www.irps.org/registration-fees). 

Please register!

IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Poster Session: Transistors

poster

Poster Session: System Electronics Reliability

Poster Session: Memory Reliability

Poster Session: Circuit Reliability and Aging

Main Track - Computer Vision

We are pleased to announce the Thirty-Eighth AAAI Conference on Artificial Intelligence (AAAI-24), which will be held in Vancouver, British Columbia at the Vancouver Convention Centre – West Building from 20-27 February, 2024.

The purpose of the AAAI conference series is to promote research in Artificial Intelligence (AI) and foster scientific exchange between researchers, practitioners, scientists, students, and engineers across the entirety of AI and its affiliated disciplines. AAAI-24 will feature technical paper presentations, special tracks, invited speakers, workshops, tutorials, poster sessions, senior member presentations, competitions, and exhibit programs, and a range of other activities to be announced.

We expect for AAAI-24 to be an in-person conference – one author of all accepted papers will be expected to present work in person unless there are exceptional circumstances that prevent this.

In order to access the AAAI-24 event page you need to register [here](https://aaai.org/aaai-conference/registration/)

AAAI 2024

The purpose of the AAAI conference series is to promote research in Artificial Intelligence (AI) and foster scientific exchange between researchers, practitioners, scientists, students, and engineers across the entirety of AI and its affiliated disciplines. 

3A - RT (Reliability Testing)

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

IRPS 2022 Main Conference 

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Zhigang Ji

11

8

Presentations

DRAM Technology under Negative Bias Temperature Instability (NBTI) : from Characterization to Physical Origin Identification

Investigation of Positive Bias Temperature Instability in advanced FinFET nodes

A New Method of Automatic Extraction of RTN and OMI-friendly implementation

Investigation of Interplays between Body Biasing and Hot Carrier Degradation (HCD) in Advanced NMOS FinFETs

Convolution-Based Vth Shift Prediction and the New 9T2C Pixel Circuit in LTPS TFT AMOLED

Understanding the Physical Mechanism of RowPress at the Device-Level in Sub-20 nm DRAM

A Thermal Profile Prediction Methodology for Nanosheet Circuits Featuring Cross-Layer Thermal Coupling Effect

CrossBind: Collaborative Cross-Modal Identification of Protein Nucleic-Acid-Binding Residues

Towards the Characterization of Full ID-VG Degradation in Transistors for Future Analog Applications

New Insight into the Aging Induced Retention Time Degradation of Advanced DRAM Technologies

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies

Stay up to date with the latest Underline news!

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