This paper addresses the correct analysis of thick-oxide devices that mimic HV periphery devices of 3DNAND. Thick oxides grown close to the STI are found to be thinner at the edges. We introduce a model that divides the oxide into three different regions with different EOTs. This explains the conflicting electrical data and highlights the role of corners on leakage and breakdown. Applying the model to different oxide-growth processes provides guidelines to limit thickness variations.

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics

We show that thanks to the existence of NBTI, pFETs can be used to build a physical reservoir. We demonstrate this using the Compact-Physical (Comphy) framework for BTI modeling and substantiate it with a gait and voice authentication example. Subsequently, a hardware demonstration reveals that only 9 pFETs are sufficient to distinguish gait signals from different subjects. Notably, this implementation obviates the need for specialized device engineering, allowing for direct utilization of CMOS technology.

Exploiting Bias Temperature Instability for Reservoir Computing in Edge Artificial Intelligence Applications

We study oxygen flow role during IGZO PVD process on high temperature PBTI in back-gated TFTs by combining light-assisted with electrical stress measurements. Oxygen flow is observed to affect the magnitude of charge trapping and hydrogen related channel doping during PBTI. We show a correlation between sub-gap DOS and oxygen flow during deposition: the larger the oxygen flow, the smaller the light response at time-zero and its increase during PBTI, despite a larger negative DVth. 

Light-assisted investigation of the role of oxygen flow during IGZO deposition on deep subgap states and their evolution under PBTI

In this paper, we examine the impact of recently introduced low thermal budget HKMG treatments on stress-induced leakage current and defect generation in pMOS devices. We also conduct time-dependent dielectric breakdown measurements to analyze Soft-Breakdown behavior and compare extrapolated lifetimes with conventional high-performance logic devices. Additionally, we explore the effects of a new low-temperature treatment that enhances the quality of the high-k (HK) layer to meet high-temperature  TDDB standards.

SILC and TDDB reliability of novel low thermal budget RMG gate stacks

NBTI of IGZO TFTs is studied using diverse devices and conditions. Four main characteristics are observed: V th shift is almost independent of V g_stress, and shows a large activation energy and a steep time kinetic, while the relaxation rate decreases with increasing temperatures. Using TCAD and modelling, these peculiar features can be explained by an oxide-field-dominated hydrogen release at gate side of the gate-dielectric, inducing additional doping and the negative V th shift.

Fundamental understanding of NBTI degradation mechanism in IGZO channel devices

We report on charge capture and emission of Metal-Oxide-Semiconductor AlGaN/AlN/GaN High-Electron Mobility Transistors (MOSHEMT). Defects in HfO2 or AlO result in significant instabilities, with dielectric-dependent emission: band alignment between high-k shallow defect levels and AlGaN conduction band enables full (Al2O3) or partial (HfO2) charge de-trapping. These findings are significant as reliability modes under DC stress also contribute at RF operating conditions.

DC Reliability study of high-k GaN-on-Si MOSHEMTs for mm-Wave Power Amplifiers

In this paper, we present an extensive comparative study of the degradation and recovery kinetics of vertical and lateral-based Ge-on-Si photodiodes. We show that the combination of defects around specific interfaces, in the presence of hot carriers, can lead to localized degradations in the depletion regions. By complementing experimental results with insights from TCAD simulations, we demonstrate the complex interplay between stress, sense conditions, and p-i-n junction types in determining the degradation kinetics.

Degradation and recovery kinetics study of vertical and lateral Ge-on-Si photodetectors

Significant enhancement of hot-carrier degradation and time-dependent dielectric breakdown by mechanical stress was observed in CMOS FETs. Mechanical stress was induced locally in the channels of p- and n-type FETs by applying a vertical load with a diamond tip of a nanoindenter. The induced GPa level stress was calculated with finite element modeling. Mechanical stress induces a piezoresistance effect in both p- and n- channels, leading to an increase in source/drain leakage and drive currents and drastic enhancement of impact ionization. This in turn results in strongly enhanced hot-carrier degradation and hot-electron-induced punch-through effects in pFETs and enhanced hot-carrier degradation and time-dependent dielectric breakdown in nFETs. 

Observation of Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress

This work shows that the complex dynamic-RON characteristics observed for highly scaled HEMT devices results from the similar capture/emission activation energies of the defects present in different epitaxial layers. This work also (i) presents an optimized experimental scheme for a detailed analysis of the different charge-trapping mechanisms in GaN-on-Si HEMTs, (ii) describes the charge-trapping kinetics over a wide range of temperatures using capture/emission time (CET) maps, and (iii) models the defect energy distribution in the AlGaN barrier by analytically deriving the 2D potential profile in the access region and combining it with the results from CET maps.

Interpretation and modelling of dynamic-RON kinetics in GaN-on-Si HEMTs for mmWave applications

This paper reports BTI trends in high-voltage transistors for memory periphery devices with SiO2/Poly and High-K/Metal gate stacks. For PBTI, we present an extension to the typical power law kinetics that is related to the creation of interface states due to hot electrons transported through the gate oxide. This extension enables a good fit of accelerated test data and, thereby, lifetime extrapolation. We then explore EOT and gate stack trends in PBTI. For NBTI, we report gate stack, EOT, and thermal budget trends.

BTI of High-Voltage Logic-for-Memory Devices

Benefitting from forksheet device co-integration with nanosheets, we evaluate the reliability concerns that come along the use of the SiN-based dielectric wall. This wall could act as a “sponge” for non-equilibrium charges during hot-carrier stress, or absorb charges resulting from the horizontal field between n- and p-type devices. In-depth analysis showed no significant charge trapping phenomena were caused by the presence of the SiN wall. Both BTI and—after accounting for processing imperfections—HCI reliability were found to be comparable. We conclude the SiN dielectric wall does not constitute an additional reliability concern for the novel FSH architecture.

Evaluating Forksheet FET reliability concerns by experimental comparison with co-integrated Nanosheets

Forksheet (FS) FETs are a novel transistor architecture consisting of vertically stacked nFET and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p- to nFET separation (p-to-n separation), thus enabling further logic cell area scaling without requiring gate length scaling. We report hot-carrier degradation (HCD) simulations of FS FETs and compare this architecture to nanowire (NW) and nanosheet (NS) FETs. HCD is shown to decrease with increasing sheet width in both NS and FS FETs when taking interface state generation into account. Considering that a FS FET can be made wider than an NS FET because of the reduced p-to-n separation, lower HCD for the FS FET is observed. Finally, we make an initial assessment of the impact of oxide defect charging in the FS wall. We confirm decreasing influence of fixed wall charge for increasing sheet widths and estimate that the overall impact of wall charging will stay under control at operating conditions.

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

Poster Session: Process Integration

poster

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

6C (Neuromorphic Computing )Reliability

technical paper

5A (Process Integration)

4A (Transistors)

4B (RF/mmW/5G)

2B (Reliability Testing)

10A - TX (Transistors)

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

IRPS 2022 Main Conference 

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Jacopo Franco

12

SHORT BIO

Presentations