We have investigated and report here for the first time time-dependent dielectric breakdown (TDDB) in 45-nm RFSOI n-channel floating body MOSFETs at cryogenic temperatures. DC constant voltage stress is applied at the gate while the substrate chuck temperature is varied from 300K down to 10K. While t63 decreases with increasing temperature, shape parameter β shows an inverted U-shaped behaviour which is explained using the bandgap model. Three levels of activation energy are seen for high, low and deep low temperatures where the activation energy decreases from high to deep low temperatures. The observed behaviour is further explained using the bandgap as per the percolation theory.

Deep Cryogenic Temperature TDDB in 45-nm PDSOI N-channel FETs for Quantum Computing Applications

The sub-THz spectrum between 100GHz and 300GHz is of great interest for achieving next generation 6G cellular network goals of ultra-high data rate, ultra-low latency and high sensing precision. Carrier frequencies &gt;100GHz create significant challenges, including higher losses, lower semiconductor device performance, and a smaller per element physical area that constrains circuit size, integration, power and thermal management. Semiconductor technologies with transistor performance &gt;500GHz are needed for improved efficiency, gain, noise and area at the front end of the 6G phased array radio. Advances in SiGe BiCMOS have the potential to increase silicon transistor performance while leveraging the cost and scale of mature high-volume silicon manufacturing for 6G sub-THz. Compound semiconductor technologies such as InP and GaN have the best front end performance at sub-THz. Advances in heterogeneous and monolithic integration with silicon are needed to address the cost and scale concerns of high frequency InP and GaN.  A comprehensive approach to reliability is essential in order to extract maximum performance without sacrificing reliability.

6G Roadmap for Semiconductor Technologies: Challenges and Advances

RF reliability of 40-nm PDSOI nFET power amplifier (PA) cell at 26.5GHz is investigated. DC and RF stresses are applied in conducting and non-conducting hot carrier stress mode to study the PA cell RF and DC degradation behaviour. The relationship between DC and large-signal RF performance under various RF stress conditions is investigated using DC and RF metrics. The degradation rate depends on RF power and terminal voltages, where ~8X lower degradation is observed at low VGS. During RF stress, the DC performance degradation rate is higher in the linear operating region than the saturation region. The impact of RF stress is amplified in the presence of DC stress, accelerating the degradation of PA cells. For different VGS under RF stress conditions, the lifetime of the PA cell is calculated and compared.

RF Reliability of CMOS-Based Power Amplifier Cell for 5G mmWave Applications

Two key mechanisms (i) trapping induced Parasitic Drain Series Resistance (PDSRI) and (ii) interface state generation Nit are both identified within non-conducting hot carrier injection (NCHCI). During NCHCI stress, the drain current degradation due to PDSRI is observed at the first time readout as a sudden shift and is followed by conventional (relatively lower) monotonically increasing shift due to interface state generation. The convolution of these two phenomena, complicates the extraction of their unique model parameters and lifetime extrapolation. Characterization methods to isolate each is demonstrated. Their separate dependencies on gate length, drain voltage, and temperature are 










studied and modeled. Using TCAD simulations, the differences in 
the damage rate and location due to PDSRI and Nit are studied. By 
understanding the E-field distribution, the charge trapping in the 
side wall spacer region is found to be the key contributor to PDSRI 
behavior under NCHCI conditions.

Fernando Guarin

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