**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9131838

**Abstract:**

This paper presents the first GC-eDRAM in 16nm FinFET technology, featuring a mixed-VT 3T gain-cell structure to minimize the storage node (SN) leakage. The implemented 1 Mbit 3T GC-eDRAM is fully logic-compatible and provides a 2X smaller bitcell size compared to a 6T SRAM with similar design rules, offering the highest density logic-compatible memory cell in 16nm technology. Measurement results demonstrate a 77 μs DRT under a 600mV VDD, which is over 10X longer than previously reported GC-eDRAMs in 28nm technologies. The memory was fully operational at temperatures spanning -40C–125C and under a supply voltage as low as 450mV, providing the lowest measured VDDmin and widest temperature range reported in the literature for GC-eDRAM.

A 1 Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16nm FinFET

**Session Chairs:** Guilhem Larrieu, Laboratory of Analysis and Architecture of Systems; Alyssa Apsel, Cornell Unveristy

B1L-6: Memories and 3D Integration (JOINT 2020 TEDbrief special edition & SSC-L special edition)

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
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* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
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JOINT PLENARY talks live broadcast: September 13, 2021 
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LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
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(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

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Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





Robert Giterman

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A 1 Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16nm FinFET

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