**Please read the paper on the following link:**

https://1worldcontent.com/ess/9101.pdf

**Abstract:**

This paper presents an energy efficient high voltage(HV) ultrasonic driver for ultrasonic haptic feedback, designed to drive Piezo electric micro machined transducers (PMUT). To achieve low power consumption while driving large capacitive load of a PMUT device, advanced charge recycling (ACR) ispresented reducing the reactive power consumption without off-chip supply generation. To facilitate ACR in a compact footprint a bidirectional high voltage switch is proposed. The ultrasonic driver is able to drive a transducer capacitance of 240pF upto 36V swing with a frequency of 250kHz, only consuming 0.2CV2f power, outperforming bulky coil-based solutions. Re-alised in a high voltage 0.18μmbulk BCD technology, the driver only occupies 0.16mm2.

A 36V Ultrasonic Driver for Haptic Feedback Using Advanced Charge Recycling Achieving 0.20CV2f Power Consumption

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9288.pdf

**Abstract:**

A new standard cell topology, Dual-Input Pseudo-CMOS (DIPC), for dual-gate Indium-Gallium-Zinc-Oxide (IGZO) thin-film transistor (TFT) technology on flexible substrates is presented. The proposed logic topology is compared with the conventional Pseudo-CMOS in terms of robustness (noise margin), speed performance, power consumption and area usage. This work shows that the back-gate of a TFT can be used as a separate parallel transistor reducing the number of devices in logic gates without compromising the speed and the power. Two 32-bit code generators for RFID transponders with both libraries have been designed and fabricated using n-type only TFTs with a channel length of 5 micrometers. The proposed topology allowed to reduce the number of TFTs by 24% and the chip consumes only 2.2 microwatt of power at 4 kHz clock frequency and 1 V of supply voltage. This work also forecasts that the number of TFTs can be reduced strongly by using the proposed DIPC topology for complex designs such as arithmetic logic units and microprocessors.

Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9112.pdf

**Abstract:**

An internally compensated, two stage operational amplifier has been presented, fabricated using a-IGZO TFT technology. The highlight of the design is a new active load circuit based on positive feedback to realize high incremental impedance. The OpAmp has been fabricated and measured to have 57 dB DC-gain, 311 kHz unity-gain frequency and 75 deg. phase margin at 2.43mW power. To our knowledge, this design reports the highest achieved performance of an operational amplifier made in a-IGZO technology.

An a-IGZO TFT Based Op-Amp with 57 dB DC-Gain, 311 kHz Unity-Gain Freq., 75 deg. Phase Margin and 2.43 mW Power on Flexible Substrate

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9269.pdf

**Abstract:**

We present a 2T0C IGZO based Capacitor-less memory that enhances the sensing margin and retention time for DRAM applications requiring higher data immunity. In the proposed technique for increased data integrity, the Read Bit-Line (RBL) is precharged at Half-VDD, instead of Full-VDD, to utilize the rising edge of read word line (RWL) at the beginning of read. This increases the storage node potential of the bit-cell (due to coupling between RWL and the storage node) which is otherwise degraded at write termination due to coupling of write word line (WWL) and the storage node.

Enhanced Data Integrity of In-Ga-Zn-Oxide Based Capacitor-Less 2T Memory for DRAM Applications

**Session Chairs:** Cédric Tubert, STMicroelectronics; Matthias Kuhl, Technische Universität Hamburg

B2L-6: Energy Efficient Sensor Interfaces

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Session Chairs:** Liesbet Van Der Perre, Katholieke Universiteit Leuven; Atila Alvandpour, Linköping University;

B3L-2: Wireless System Digital Interface & Building Blocks

**Session Chairs:** Jens Anders, University of Stuttgart; Carolina Mora Lopez, IMEC;

E1L-2: Amplifiers

**Session Chairs:** Qing-Tai Zhao, Forschungszentrum Jülich; Tortorelli Innocenzo, Micron Technologies

Wim Dehaene

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OTHER AFFILIATIONS

Presentations

A 36V Ultrasonic Driver for Haptic Feedback Using Advanced Charge Recycling Achieving 0.20CV2f Power Consumption

Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates

An a-IGZO TFT Based Op-Amp with 57 dB DC-Gain, 311 kHz Unity-Gain Freq., 75 deg. Phase Margin and 2.43 mW Power on Flexible Substrate

Enhanced Data Integrity of In-Ga-Zn-Oxide Based Capacitor-Less 2T Memory for DRAM Applications

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