**Please read the paper on the following link:**

https://1worldcontent.com/ess/9156.pdf

**Abstract:**

We present Thestral, a 10-core RISC-V chip for energy-proportional parallel computing manufactured in 22nm FD-SOI technology, featuring a control core and a nine-core compute cluster, with specialized units for floating-point (FPU) and integer (IPU) extensions. Each FPU, IPU, and the whole cluster can be independently power-gated with a sub-10 ns power-up sequence, allowing fine-tuning of leakage vs. dynamic power ratio. We achieve up to 42% measured power savings in a low-power, near-threshold operating point (@350 MHz, 0.6V, 25 °C). In a high-performance operating point (@850 MHz, 0.9V, 75 °C), a many-core Thestral may save up to 41% power during memory-bound application phases.

A 10-Core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing Over a Wide Voltage and Temperature Range

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9143.pdf

**Abstract:**

IoT end-nodes require extreme performance andenergy efficiency coupled with high flexibility to deal with theincreasing computational requirements and variety of mod-ern near-sensor data analytics applications. Low-Bitwidth andMixed-Precision arithmetic is emerging as a trend to addressthe near-sensor analytics challenge in several fields such aslinear algebra, Deep Neural Networks (DNN) inference, andon-line learning. We present Dustin, a fully programmableMultiple Instruction Multiple Data (MIMD) cluster integrating16 RISC-V cores featuring 2b-to-32b bit-precision instruction setarchitecture (ISA) extensions enabling fine-grain tunable mixed-precision computation. The cluster can be dynamically configuredin Vector Lockstep Execution Mode (VLEM), turning off all IFstages except one, reducing power consumption by up to 38%with no performance degradation. The cluster, implemented in65nm CMOS technology, achieves a peak performance of 58GOPS and a peak efficiency of 1.15 TOPS/W.

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

**Session Chairs:** Christoph Studer, ETH Zürich; Kathy Wilcox, Advanced Micro Devices, Inc.

B3L-3: High Performance Computing & Monitoring

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
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ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





Luca Benini

2

2

Presentations

A 10-Core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing Over a Wide Voltage and Temperature Range

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

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