**Please read the paper on the following link:**

https://1worldcontent.com/ess/9217.pdf

**Abstract:**

This paper presents a high-bandwidth, high-resolution continuous-time incremental sigma-delta modulator employing a finite impulse response (FIR) filter in the feedback for improved clock jitter immunity. The paper proposes a new scheme to alleviate the aggressive overshoots in the incremental regime. Besides, the presented design features a new implementation technique for the dual-RTZ approach in FIR resistive DACs to eliminate inter-symbol interference (ISI) errors. The presented prototype is fabricated in 180-nm CMOS technology and achieves a dynamic range (DR) of 90.3 dB and a peak spurious-free DR of 93.1 dB at a Nyquist conversion rate of 1 MS/s.

A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9256.pdf

**Abstract:**

This paper presents a single-chip high-voltage transceiver ASIC for low-ﬁeld NMR spectroscopy. The chip integrates an adjustable high-voltage (HV) H-bridge power ampliﬁer (PA) with a PLL frequency synthesizer and a quadrature low intermediate frequency (low-IF) receiver, achieving a measured input-referred voltage noise density of 1.1 nV/√Hz. The operating frequency of the chip is from 0.1 MHz to 200 MHz, supporting all relevant Larmor frequencies for low-ﬁeld mobile and portable NMR. The PA consists of four isolated 50 V NMOS transistors, isolated gate drivers with a digitally adjustable deadtime control, high-frequency level shifters, and a TX-control logic that supports bootstrapping of the integrated high-side drivers. The output current can be deﬁned by an adjustable voltage supply from 0 V to 50 V, delivering a maximum current of 2.0 A_pp into a non-tuned 3 mm NMR coil and up to 8.3 A_pp into a parallel tuned NMR coil. Inside a custom-designed 1.1 T portable NMR magnet, the system achieves a spin sensitivity of 1.1 × 10^16 spins/√Hz and a concentration sensitivity of 1 mM/√Hz.

A 0.1 MHz to 200 MHz High-Voltage CMOS Transceiver for Portable NMR Systems with a Maximum Output Current of 2.0 App

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9211.pdf

**Abstract:**

We present a tunneling magnetoresistive (TMR) sensing microsystem consisting of a low flicker noise TMR sensor and a custom integrated readout frontend. The proposed sensor readout circuit introduces a novel ultra-low-noise current biasing scheme for the TMR sensor, which achieves a very low current noise floor of 2.2 pA/sqrt(Hz) for a 1mA biasing current. The TMR output voltage is processed by a differential readout scheme to improve the baseline-to-signal ratio. The microsystem also features an on-chip 10-bit current DAC that allows compensating for the large process variations in the TMR base resistance value. The readout chip is manufactured in a 180nm SOI CMOS technology and heterogeneously integrated with the TMR sensor. The readout chain provides a thermal noise floor of 4 nV/sqrt(Hz), while, together with the biasing scheme, consuming a total power of 38mW. The complete sensor system consisting of the TMR and the readout circuit provides a state-of-the-art magnetic field noise floor of 120 pT/sqrt(Hz).

A Readout Circuit for Tunnel Magnetoresistive Sensors Employing an Ultra-Low-Noise Current Source

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9123.pdf

**Abstract:**

We present a widely tunable transimpedance amplifier (TIA) with a dc servo loop and an optional bandwidth extension. All resistors are implemented as multi-element pseudo-resistors, which feature high linearity, robustness against process and temperature, and a very wide tuning range of more than five decades. The TIA features a noise floor of 0.6fA/sqrt(Hz) at its maximum transimpedance of 150GOhm and a bandwidth of 2.9MHz at its minimum transimpedance of 440kOhm. A subsequent inverting amplifier stage provides an optional pole-zero compensation to extend the TIA\'s overall bandwidth. An additional dc servo loop can be used to compensate large dc currents.

A 440-kOhm to 150-GOhm Tunable Transimpedance Amplifier Based on Multi-Element Pseudo-Resistors

**Session Chairs:** Georges Gielen, Katholieke Universiteit Leuven; Venkatesh Srinivasan, Texas Instruments

B2L-3: Oversampled ADC

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Session Chairs:** Viola Schaffer, Texas Instruments; Makoto Nagata, Kobe University

D1L-6: Analog Techniques

**Session Chairs:** Jens Anders, University of Stuttgart; Carolina Mora Lopez, IMEC;

Jens Anders

4

33

1

Presentations

A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC

A 0.1 MHz to 200 MHz High-Voltage CMOS Transceiver for Portable NMR Systems with a Maximum Output Current of 2.0 App

A Readout Circuit for Tunnel Magnetoresistive Sensors Employing an Ultra-Low-Noise Current Source

A 440-kOhm to 150-GOhm Tunable Transimpedance Amplifier Based on Multi-Element Pseudo-Resistors

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES