**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9169659

**Abstract:**

This work presents the first on-chip bio-inspired reservoir computer (RC) prototype implemented in 65nm CMOS. The RC comprises 50 time-multiplexed neurons, and each neuron embeds a strong non-linearity in a feedback loop. The RC applies a non-linear transformation to the input and projects it to high-dimensional space, thus allowing linear separation by a simple logistic regression (LR) layer implemented off-chip. We demonstrate real-time stress detection from electrocardiogram (ECG) signals using the RC. The RC achieves 93% classification accuracy, which is 6% better than state-of-the-art digital classifiers. Operating at 40kHz, the prototype consumes 27.5nJ/classification, which is 7x lower than state-of-the-art ECG processors performing similar complexity classification tasks.

A Bio-Inspired Reservoir-Computer for Real-Time Stress Detection from ECG Signal

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9261.pdf

**Abstract:**

This work presents the first on-chip, mixed-signal echo state network (ESN) for the early prediction of heart disease. The ESN comprises an input layer, a non-linear projection (NP) layer, and an output layer. Only the output layer of the ESN requires training. The input layer weights are time-invariant and drawn from a static binary random distribution. Thus, the proposed ESN has significantly lower trainable parameters than other non-linear neural networks used for similar prediction tasks. A 65nm prototype is validated with the Cleveland Heart Disease (CHD) dataset. The ESN achieves a mean accuracy of 84.6% over 5 test chips while consuming 7.5nJ energy/inference.

7.5nJ/Inference CMOS Echo State Network for Coronary Heart Disease Prediction

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9145702

**Abstract:**

This work presents a true random number generator (TRNG) based on a stochastic delta-sigma modulator (DSM) with ring oscillator (RO) integrators. The TRNG leverages noise and jitter in the ROs as an entropy source. A multi-bit non-return to- zero (NRZ) digital-to-analog converter (DAC) in the feedback path ensures DSM noise dominates input swing seen by the frontend integrators. Hence, the DSM can concurrently operate as an ADC and TRNG. A 65nm prototype achieves Shannon entropy > 0.999998 with lower-bound min-entropy > 0.995 at 52Mbps throughput while passing all NIST tests across multiple chips and voltage/temperature corners without needing calibration. The combined power consumption of ADC and TRNG is 0.36mW which is the lowest among state-of-the-art RO TRNGs. Low power consumption, high entropy, and concurrent operation of the TRNG as an ADC are principal contributions of this work.

0.36mW, 52Mbps True Random Number Generator Based on a Stochastic Delta-Sigma Modulator

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9178737

**Abstract:**

A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this work. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring-oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of signal-band and also has intrinsic interferer rejection capability. A prototype ADC fabricated in 65nm CMOS is operated at an IF of 52MHz. The ADC has an SNDR of 63.1dB and 59.5dB at 1.04MHz and 4.3MHz bandwidth, respectively. The ADC consumes only 0.36mW power from a 0.9V supply and has an energy efficiency of 21fJ/step improving upon the current state-of-the-art by 3.5x.

21fJ/Step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC

Spiking neural network (SNN) is promising but the development has fallen far behind conventional deep neural networks (DNNs) because of difficult training. To resolve the training problem, we analyze the closed-form input-output response of spiking neurons and use the response expression to build abstract SNN models for training. This avoids calculating membrane potential during training and makes the direct training of SNN as efficient as DNN. We show that the nonleaky integrate-and-fire neuron with single-spike temporal-coding is the best choice for direct-train deep SNNs. We develop an energy-efficient phase-domain signal processing circuit for the neuron and propose a direct-train deep SNN framework. Thanks to easy training, we train deep SNNs under weight quantizations to study their robustness over low-cost neuromorphic hardware.  Experiments show that our direct-train deep SNNs have the highest CIFAR-10 classification accuracy among SNNs, achieve ImageNet classification accuracy within 1% of the DNN of equivalent architecture, and are robust to weight quantization and noise perturbation.

Temporal-Coded Deep Spiking Neural Network with Easy Training and Robust Performance

This poster presents a technique to leverage artificial intelligence (AI) to reduce energy transmission in image sensor networks. A multi-task learning analog AI circuit will be embedded in CMOS image sensor to 1) identify relevant frames for transmission; and  2) perform image compression before transmission. Initial measurements results in 65nm process are demonstrated on low-resolution MNIST dataset. The analog AI classifier achieves state-of-the-art energy efficiency.

https://underline.io/speakers/59512-arindam-sanyal

On-chip Multi-Task Learning Analog Artificial Intelligence For Low-Cost Image-Based Environmental Monitoring

**Session Chairs:** Minhao Yang, École Polytechnique Fédérale de Lausanne; Mirjana Banjevic, Sensirion AG

B3L-1: Imaging, MEMS, Sensors (JOINT 2020 TEDbrief special edition & SSC-L special edition)

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Session Chairs:** Antoine Frappé, Institut Supérieur de l'Électronique et du Numérique; Marian Verhelst, Katholieke Universiteit Leuven

D1L-1: Ultra Low Power Neural Network CMOS Accelerators

**Session Chairs:** Liesbet Van Der Perre, Katholieke Universiteit Leuven; Atila Alvandpour, Linköping University

E2L-4: Digital Design Solutions for Wireless Communications (ESSCIRC 2020 SSC-L special edition)

**Session Chairs:** Mattias Palm, Ericsson; Turner Walker, Nvidia Corporation

E3L-3: Data Converters & Chip-to-Chip Interfaces (ESSCIRC 2020 SSC-L special edition)

Main Track

The purpose of the AAAI conference is to promote research in artificial intelligence (AI) and scientific exchange among AI researchers, practitioners, scientists, and engineers in affiliated disciplines. 

AAAI 2021

You are welcome and encouraged to view the posters and start asking questions in the Q&A boxes next to each of them. 

Break/Poster Presentations 1

poster

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


Arindam Sanyal

6

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SHORT BIO

Presentations

A Bio-Inspired Reservoir-Computer for Real-Time Stress Detection from ECG Signal

7.5nJ/Inference CMOS Echo State Network for Coronary Heart Disease Prediction

0.36mW, 52Mbps True Random Number Generator Based on a Stochastic Delta-Sigma Modulator

21fJ/Step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC

Temporal-Coded Deep Spiking Neural Network with Easy Training and Robust Performance

On-chip Multi-Task Learning Analog Artificial Intelligence For Low-Cost Image-Based Environmental Monitoring

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