Recent advancements and applications in compact phased arrays, MIMO basestations and handsets, automotive radar, etc. are driving the need for RF power generation in CMOS technologies to accomodate high complexity systems that require RF output power. This presentation will provide an overview of CMOS device concepts up to architectural choices that have been proposed to improve RF power and efficiency in CMOS technologies. This discussion focuses on RF power amplifier concepts.

Overview of RF Power Generation Using CMOS Technologies

This poster introduces a proposed automated design approach for low-cost, turnkey integrated power converters that includes integrated built-in self-test (BIST) to increase the occurrences of first-pass design success. This automation could bridge the gap between the conflicting needs for rapid design cycles and high-performance power electronics seen in applications such as mobile handsets, IoT, and wearables. The goal is to enable rapid design of low-to-medium power converters by developing an automated design platform. By using the BIST monitoring data to update the statistical models used during the design phase, multiple design development cycles could be eliminated and the design risk and non-recurring cost (NRE) could be significantly reduced. It is expected that these closed-loop systems would be successfully automated through creation of analytical models of power converter architectures, development of a circuit component design library and a circuit simulation methodology for collecting a representative subset of design parameters that will correlate to the relevant performance space, creation of statistical models and data that can be used to fit to geometric programming (GP) and support vector machine (SVM) algorithms, and development of a computationally efficient and accurate optimization approach. 

https://underline.io/speakers/59509-jennifer-kitchen

Design Automation Approach for Integrated Power Electronics

**Wednesday, September 22nd**

**Session Chairs**: Yvan Morandini *Soitec*  and Eric Mercier *CEA*

RF-SOI technology is becoming a standard for cellular and connectivity RFFE technologies across the last ten years. Fully depleted silicon-on-insulator (FD-SOI) is gaining ground and setting low power and RF/mmW technology standards. RF/mmW systems are facing new challenges across a number of new markets, such as IoT, automotive, 5G from sub 6GHz to millimeter wave bands. SOI technology offers remarkable device performances in terms of power, performance, area and cost tradeoffs (PPAC). In high-data rate communications like RF and millimeter-wave devices,RF-SOI and FD-SOI enable high performance platforms from RF Front End to System On Chip including numerous unique advantages making it most likely the best in class RF-CMOS technologies on the market.

This technical workshop will cover the RF-SOI and FD-SOI technology platforms with a focus on its compatibility with RF & mmWave communications. Attendees will hear from SOI experts from leading industry and research institutions presenting updates on key SOI technology developments and building blocks across the semiconductor value chain. Topics will include substrate material and  device fundamentals, modeling and simulation and characterization of RF/mmW devices and circuits. The workshop will give an overview about how SOI technology is benefiting current and future broad end user applications.

9. SOI technology and design challenges for RF and mmWave: from Front-End Modules to SoC

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

ESSCIRC ESSDERC Educational Events

The Educational Events of ESSCIRC ESSDERC 2021. 

You are welcome and encouraged to view the posters and start asking questions in the Q&A boxes next to each of them. 

Break/Poster Presentations 1

poster

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


Jennifer Kitchen

2

6

SHORT BIO

Presentations

Overview of RF Power Generation Using CMOS Technologies

Design Automation Approach for Integrated Power Electronics

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