Development of complementary metal–oxide–semiconductor (CMOS) logic is expected to approach its fundamental limit as the scaling down of the CMOS technology is reaching an end. As a route to extend the technology roadmap beyond traditional CMOS logic, novel spin-based logic architectures are being developed to provide nonvolatile data retention, near-zero leakage, and scalability. In particular, architectures based on magnetic domain walls (DWs) take the advantage of the fast motion, high density, non-volatility and flexible design of DWs to process and store information [1,2]. Such schemes have so far relied on DW manipulation and clocking using an external magnetic field, which hinders their implementation in dense, large-scale chips. Here we demonstrate a method for performing all-electric logic operations and cascading using DW racetracks [3]. Our concept for the magnetic DW logic is based on efficient DW motion induced by spin-orbit torques (SOTs) [4] and recently developed chiral coupling between adjacent magnets where the magnetic anisotropy competes with the interfacial Dzyaloshinskii–Moriya interaction (DMI) [5,6]. First we created a DW inverter, the essential basic building block for all implementations of Boolean logic, by embedding a narrow in-plane magnetized region in a racetrack with out-of-plane magnetization and demonstrate the operation of the DW inversion on application of an electric current (Fig. 1a). Building on the principles used to construct the DW inverter, we then fabricated reconfigurable NAND and NOR logic gates, making our concept for current-driven DW logic functionally complete. Finally, we cascaded several NAND gates to build XOR and full adder gates, demonstrating electrical control of magnetic data and device interconnection in logic circuits (Fig. 1b). Our work provides a viable platform for scalable all-electric magnetic logic, paving the way for memory-in-logic applications.References: [1] Allwood, D. A. et al. Science 309, 1688–1692 (2005). [2] Parkin, S. & Yang, S.-H. Nature Nanotechnol. 10, 195–198 (2015). [3] Luo, Z. et al. Nature 579, 214-218 (2020). [4] Manchon, A. et al. Rev. Mod. Phys. 91, 035004 (2019). [5] Luo, Z. et al. Science 363, 1435 (2019). [6] Dao, P. D. et al. Nano Lett. 19, 5930-5937 (2019).

Current-driven magnetic domain-wall logic INVITED

R3: MRAM, Magnetic Logic, and Related Devices

technical paper

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Zhaochu Luo

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Current-driven magnetic domain-wall logic INVITED

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