In this work, H3TRB testing is conducted to compare the accelerated failure of vertical SiC power MOSFETs provided by two-well known manufacturers. A pronounced drain-to-source leakage is observed in tested devices from only one of the manufacturers, which is associated with a surface charge accumulation near the edge-termination structure of the device. Failure analysis of the device and package encapsulant is conducted to investigate the failure/degradation mode and to better understand the reliability physics. 

Surface Charge Migration in SiC Power MOSFETs Induced by High-Voltage H3TRB Testing

Gallium nitride (GaN) MOSCAPs and MOSFETs are often investigated for high-power applications ranging from electric vehicles to photovoltaic invertors and smart electric grids. The specific material properties of GaN, including its wide bandgap, higher obtainable breakdown voltages, and higher electron mobilities, enable novel advantages not attainable using traditional silicon power devices. Among the many challenges reported for vertical GaN MOSFETs, optimization of the semiconductor/dielectric interface is crucial to improve important parameters such as threshold voltage, leakage currents, and interface trap densities (DIT). Previous work on GaAs has shown the importance of GaxOy mitigation through sequenced TMA purging for improved interfaces but has not elaborated on the impact of this on electrical output characteristics. For GaN, to date little work has been published that analyzes the impact of minimized interfacial GaxOy from optimized ALD techniques and its effect on electrical performance in MOS devices. Minimizing GaxOy formation at the semiconductor-dielectric interface is necessary to obtain optimal performance in GaN MOS structures. The fundamental understanding of the impact of improved oxide deposition techniques for GaN MOSFET gates is critical to accurately describe device performance. Relative improvements to dielectric leakage, DIT distributions, and capacitance-voltage (C-V) trends may be analyzed to understand how each is affected through the elimination of native oxide concentrations at the interface of GaN MOSFET gates. This study analyzes changes in electrical performance of Al2O3 dielectrics fabricated using atomic layer deposition (ALD) techniques on GaN epilayers grown on bulk GaN substrates (GaN-on-GaN). Traditional ALD deposition techniques for aluminum oxide (Al2O3) utilize reactions of trimethyl aluminum (TMA) and water to form dielectric films on various substrates. Previous studies have shown that gallium oxide (GaxOy) formation on gallium arsenide (GaAs) can be alleviated by cycling TMA purges during ALD deposition to control oxidation states and mitigate Ga-O and As-O bonding. For GaN, improvements to gate interfaces of high-k dielectrics such as Al2O3 are crucial to ensure optimal switching and electrical response of complex vertical GaN MOSFETs. Leakage currents and high densities of interfacial traps have been shown to reduce device performance in previous studies. This work shows improved C-V responses of ALD Al2O3 films using quasi-static capacitance measurements. Optimized films were fabricated by the mitigation of GaxOy at the semiconductor/dielectric interface. Films grown on substrates that did not receive a TMA dose prior to the H2O precursor for ALD growth of Al2O3 films show a significantly higher amount of native oxide between the semiconductor and gate dielectric. The relative percentage of native oxide found at the interface is quantified via x-ray photoelectron spectroscopy (XPS) and shows a significant reduction following TMA purges. This improved ALD technique for Al2O3 deposition also shows a reduction of mid-gap trap states and hysteresis observed during C-V testing which further indicates improved interface quality and electrical response of the tested devices. Relative improvement to film quality is dependent upon improved gate dielectric deposition techniques which diminish GaxOy concentration at the semiconductor/dielectric interface. The impact of gate interfaces on GaN MOS devices is directly linked to calculated DIT, leakage currents, and other important electrical characteristics which must be optimized on simple device structures prior to implementation in complex architectures such as vertical GaN MOSFETs.

Improving Electrical Performance of GaN-on-GaN MOS Devices Via Optimized Atomic Layer Deposition of Al2O3 Gate Dielectrics

In order to evaluate the time evolution of avalanche breakdown in wide and ultra-wide bandgap devices, we have developed a cable pulser experimental setup that can evaluate the time-evolution of the terminating impedance for a semiconductor device with a time resolution of 130 ps. We have utilized this pulser setup to evaluate the time-to-breakdown of vertical Gallium Nitride and Silicon Carbide diodes for possible use as protection elements in the electrical grid against fast transient voltage pulses (such as those induced by an electromagnetic pulse event). We have found that the Gallium Nitride device demonstrated faster dynamics compared to the Silicon Carbide device, achieving 90% conduction within 1.37 ns compared to the SiC device response time of 2.98 ns. While the Gallium Nitride device did not demonstrate significant dependence of breakdown time with applied voltage, the Silicon Carbide device breakdown time was strongly dependent on applied voltage, ranging from a value of 2.97 ns at 1.33 kV to 0.78 ns at 2.6 kV. The fast response time (< 5 ns) of both the Gallium Nitride and Silicon Carbide devices indicate that both materials systems could meet the stringent response time requirements and may be appropriate for implementation as protection elements against electromagnetic pulse transients.

Reverse Breakdown Time of Wide Bandgap Diodes

This study analyzes the changes in the density of interface traps (DIT) for various atomic layer deposition (ALD) gate dielectric films on gallium nitride (GaN) devices fabricated on bulk GaN substrates. Each film type has been chosen with an optimized insulator/semiconductor interface obtained through chemical cleans or post deposition annealing (PDA). Reduction in dielectric leakage and interface traps in MOSCAP devices may be used in order to understand how these mechanisms affect more complex devices such as vertical GAN MOSFETs. GaN MOSFET and MOSCAP devices are often investigated and implemented in power systems with applications ranging from electric vehicles (EVs) to smart power grids. The unique material properties of GaN such as wide bandgap, high breakdown voltage, and high electron mobility create unique advantages over traditional silicon FETs. Vertical GAN MOSFETs are better suited for higher voltage applications due to current flow and voltage drop perpendicular to the surface while also reducing required chip area for high operating voltages. Although there are many advantages of vertical GaN devices, such an architecture presents unique challenges that must be addressed before such devices may be implemented in high power applications, such as the requirement for a native substrate and the need to improve the gate dielectric interface. The interface between the gate dielectric and the semiconductor is crucial in order to reduce threshold voltage drift, leakage current, and the density charge traps. Previous work has shown the importance of DIT reduction with chemical cleans and PDAs. Accurate calculations of the density of interface traps (DIT) are vital to fully realize device operation and reliability. The choice between surface cleans and dielectric annealing as a leakage reduction technique is dependent on the material and available processing capabilities. While PDAs may reduce the dielectric breakdown strength, they have been found to reduce gate leakage current and improve device performance for most gate dielectrics. Several methods have been proposed for DIT characterization, including the voltage dependencies of low- and highfrequency capacitance (CV), conductance (GV), and surface potential (WY). DIT may be calculated from the surface potential of the dielectric using the quasi-static capacitance and the capacitance of the chosen gate dielectric. This work uses quasi-static CV and surface potential electrical characterization of GAN MOSCAPs to determine DIT of various gate dielectric materials treated with PDAs and chemical cleans. Optimization of such films on MOSCAPs will allow for implementation into vertical GAN MOSFET architectures. Interface trap density may be reduced by decreasing the capacitance associated with defects and surface contamination or by selection of a dielectric material with a lower dielectric constant. Fixed charges at the dielectric/semiconductor interface are manifested in hysteresis between forward and reverse voltage sweeps and may be the result of contamination prior to ALD or point defects in the material. Al,0. is an attractive gate dielectric material due to its dielectric constant, which may improve breakdown strength (Fig. 1), but it may suffer from higher memory charge between continuous bias sweeps. SiO, ALD films have lower breakdown and significantly lower leakage currents but show the lowest density of remaining fixed charges between sweeps, suggestive of the lowest DIT of the tested dielectrics (Fig. 2) with the addition of PDA. Results were verified by altering bias conditions during testing in order to accumulate and deplete interface charges. Minor plateaus in capacitance in forward bias indicate the presence of negative fixed interface charges. Additional characterization may be necessary to determine the optimal conditions for DIT reduction for HfO., films, including reduction in PDA temperatures in combination with improved substrate chemical cleans.

Interface Trap Density Characterization of ALD Gate Dielectrics for GaN Power MOSFETs

Movement of Current Filaments and its Impact on Avalanche Robustness in Vertical GaN P-N diode Under UIS stress

This work reports an on-wafer study of avalanche behavior and failure analysis of in-house fabricated 1.3 kV GaN-on-GaN P-N diodes. DC breakdown is measured at different temperatures to confirm avalanche behavior. Diode’s avalanche
ruggedness is measured directly on-wafer using a modified unclamped inductive switching (UIS) test set-up with an integrated thermal chuck and high-speed CCD for real-time imaging during the test. The avalanche ruggedness of the GaN P-N diode is evaluated and compared with a commercial SiC Schottky diode of similar voltage and current rating. Failure analysis is done using SEM and optical microscopy to gain insight into the diode’s failure mechanism during avalanche operation.

On-Wafer Investigation of Avalanche Robustness in 1.3 kV GaN-on-GaN P-N Diode Under Unclamped Inductive Switching Stress

This study analyzes the ability of various processing techniques to reduce leakage current in vertical GaN MOS devices. Careful analysis is required to determine suitable gate materials in GaN MOSFETs since they are largely responsible for determination of threshold voltage, gate leakage reduction, and number of interface traps. SiO2, Al2O3, and HfO2 films were deposited by atomic layer deposition and subjected to treatments nominally identical to those seen in vertical GaN MOSFET fabrication. This work determines mechanisms for reducing gate leakage by reduction of surface contaminants and interface traps using pre-deposition cleans, elevated temperature depositions, and post-deposition anneals. Al2O3 is an ideal candidate for a MOSFET gate dielectric with a breakdown electric field near 802 MV/cm which is an improvement on other reported breakdown strengths for similar films. SiO2 films treated with an 850 C anneal for 30 minutes show significant reduction in leakage current densities while maintaining breakdown at 5.4 MV/cm. HfO2 films show higher sensitivity to high temperature annealing suggesting more research into surface cleans is necessary prior to incorporation into a vertical GaN MOSFET process.

Analysis of ALD Dielectric Leakage in Bulk GaN MOS Devices

This work investigates both avalanche behavior and failure mechanism of 3 kV GaN-on-GaN vertical P-N diodes, that were fabricated and later tested under unclamped inductive switching (UIS) stress. The goal of this study is to use the particular avalanche characteristics and the failure mechanism to identify issues with the field termination and then provide feedback to improve the device design. DC breakdown is measured at the different temperatures to confirm the avalanche breakdown. Diode’s avalanche robustness is measured on-wafer using a UIS test set-up which was integrated with a wafer chuck and CCD camera. Post failure analysis of the diode is done using SEM and optical microscopy to gain insight into the device failure physics.


Robert Kaplar

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