"**Please read the paper on the following link:**

https://1worldcontent.com/ess/9226.pdf

**Abstract:**

Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJ) are devices featuring stochastic properties. They are promising candidates for non-volatile memory or true random number generators. To design reliable hybrid CMOS circuits including STT-MTJs, one needs to use a compact model accounting for its stochasticity in the circuit simulations. This paper proposes a compact model that accurately mimics the MTJ stochastic switching behavior and meets the needs of fast execution time. The relevance of such a model together with its fast execution velocity are illustrated with a bitstream generator.

Fast Behavioral VerilogA Compact Model for Stochastic MTJ

Stochastic computing has recently gain attention mainly due to its low cost, fast and energy efficient circuit level implementations. In addition, it is rather fault-tolerant and noise resilient. The success of stochastic computing is due to the fact that complex functions are extremely difficult to be implemented by conventional binary logic design while they can be effectively approximated by stochastic computing. Stochastic computing uses probabilistic representation of real-valued numbers. It represents and processes numbers thanks to bitstreams. Such a stream represents the number p if the proportion of digit 1 in the stream is equal to p [1]. One of the major requirements for accurate stochastic computation is to use non-repeating and uncorrelated random number generators to produce the bitstreams. In pure digital conventional circuits, such randomness arises from Linear Feedback Shift Register (LFSR) based Random Number Generator (RNG). They output a bitstream that represents the quantity 0.5, and is then processed to represent whatever number [1]. However, LFSRs are made of CMOS logic gates and flip-flops. The produced bitstream is totally predictable, requires an important amount of energy along with a high silicon area. Recently, nanoscale devices such as Magnetic Tunnel Junctions (MTJ) have been considered for bistream generators due to their inner randomness [2]. The so-designed circuits produce pure random bitstreams (the sequence is not deterministic), and they operate in a very energy efficient way. The MTJ is a structure in which a binary information is stored as the relative direction of the magnetization of a magnet with respect to a reference one. The behaviour of this magnetization depends in part on thermal fluctuations [2], which can be leveraged as a source of stochasticity. Two types of schemes have been proposed for an MTJ based bitstream generator. First, a MTJ based RNG [3-5]: a sequence of bits ‘0’ and ‘1’ with a proportion of 50% each is generated, then processed to produce the bitstream. Second, a programmable circuit tunes the MTJ in such way that it generates directly the required bitstream, without the need of any post-processing [6]. Its implementation implies less hardware cost. However, full circuit implementation of the second scheme has not been proposed so far. In this work, we designed a bitstream generator composed of a single MTJ, a writing circuit, a reading circuit and a feedback loop. The operating principle, schematically represented in Figure 1, is the following: a current passes through the writing path of the MTJ (that has been previously set in the logic state “0”) during a short period with a specific amplitude. This brings about a probability (denoted p) that the magnetization experiences a switching. After repeating the process N times, the resulting bitstream is composed of an average of Np bit seen as “1”. The obtained bitstream then represents the number p in its stochastic representation. The reading circuit, similar to the latch-type voltage-mode sense amplifier published in [7], designed and optimized to allow asynchronous operations for low power operation, has the advantage that the static currents required to measure the resistance of the MTJ last a very short time, allowing for important energy saving. The inner CMOS based latch decorrelates the output of the reading circuit to the MTJ so that the state of the read MTJ is stored and remains available after the reading process, while the MTJ can be used again. The feedback loop, connected to the output of the reading circuit extracts the number that is represented by determining the ratio of bits at “1” and “0”. It determines the gap between the number that is computed with respect to the one that is to be represented. In the case of a large gap, the writing current is modified accordingly. This current is increased if the there are too many “0”s, and reversely it is decreased when there are too many “1”s. The writing unit is connected in series to the writing path of the MTJ. It aims at imposing a current through the writing path that is determined by the feedback loop. It is made of several transistors in parallel, acting like independent current sources. This configuration allows the circuit to find the proper writing current required for a given bitstream. This also allows handling temperature dependence of the writing current. Indeed, with temperature variation the writing current may vary in time. In our proposed circuit, the real-time tracking of the optimal writing current by the proposed feedback loop handles this problem. In conclusion, we propose an innovative single MTJ based bitstream generator leveraging the unique stochastic properties of the magnetization of the storage layer. The critical issue of PVT variations and noise are solved by our system thanks to the feedback loop and to the versatility of the writing circuit that allow for the generation of a relevant writing current that can be generalized to any bitstream computation. This study opens the way to the design of fast and energy efficient stochastic computing based circuit.

**References:**

[1] A. Alaghi and J. P. Hayes, ACM Trans. Embed. Comput. Syst [2] W. Brown, Phys. Rev. 130 (1963) 1677-1685 [3] Akio Fukushima et al 2014 Appl. Phys. Express 7 083001 [4] F. Ouattara, A. Nejat and L. Torres, IEEE Access, vol. 7, pp. 59271-59277, 2019 [5] S. Oosawa, T. Konishi and N. Onizawa, IEEE 13th International New Circuits and Systems Conference (NEWCAS), Grenoble, 2015, pp. 1-4 [6] LA de Barros Naviner et al., 13th IEEE International New Circuits and Systems Conference (NEWCAS), 2015 [7] H. Zhang, W. Kang and, IEEE Access, vol. 6, pp. 64250–64260

**Images:**

![](https://assets.underline.io/uploads/markdown_image/1/image/6719b321db54b403c7f441a57764f6a8.jpg)
Fig.1 : Schematic of the bitstream generator

 Hardware Implementation of a Magnetic Tunnel Junction based Bitstream Generator for Stochastic Computing

**Session Chairs:** Wladek Grabinski, MOS-AK Association; Viktor Sverdlov, Technische Universität Wien

D3L-5: Simulation & Modeling for Memory & Imaging Applications

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Fast Behavioral VerilogA Compact Model for Stochastic MTJ

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