The impact of Program/Erase (P/E) cycling on Cell VT Distribution (CVD) during retention bake in 3-D NAND Charge Trap Flash (CTF) arrays is modeled. Experimental data under Solid Pattern (SP) test is analyzed using Activated Barrier Double Well Thermionic (ABDWT) model. Only two adjustable parameters can model DR loss across various P/E cycles, Bake Temperature (BT), Programming Levels (PL) and CVD levels (sigma). The relative contributions from the underlying physical mechanisms are determined.

Modeling of Post-Cycling Retention Bake in 3-D CTF TLC NAND Arrays

3A (Memory Reliability)

technical paper

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**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

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Modeling of Post-Cycling Retention Bake in 3-D CTF TLC NAND Arrays

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