profile picture

Luca Larcher

Applied Materials Inc., Italy

reliability

fefet

ginestra

hzo

retention

modelling

degradation

ferroelectric

passivation

modeling

defects

igzo

breakdown

transistor

rram

5

presentations

9

number of views

SHORT BIO

Gaurav Thareja is Head of Logic and Memory Process Integration in the Metals Deposition Products division of the Semiconductor Products Group at Applied Materials, Santa Clara, USA. With a prolific career, he has made significant contributions to semiconductor device processes and materials technology. He is a recognized inventor, holding 40+ US patents, and having authored more than 30 publications and many invited talks. He received PhD in Electrical Engineering from Stanford University and has over 15 years of experience in the semiconductor industry, previously with an AI startup in bay area (Founding team and COO), High performance logic for 7/3/2nm... 

Presentations

Characterization and multiscale modeling of TDDB in state-of-the-art BEOL

Andrea Palmieri and 24 other authors

Blocking oxide material engineering to improve retention loss in 3D NAND: a modeling process optimization study

Tommaso Rollo and 4 other authors

Low-PBTS defect-engineered high-mobility metal-oxide BEOL transistors

Bastien Beltrando and 11 other authors

Reliability of non-volatile memory devices for neuromorphic applications: a modeling perspective

Andrea Padovani, Communications Chair and 6 other authors

Electron-assisted switching in FeFETs: MW dynamics – retention - trapping mechanisms and correlation

Milan Pesic and 5 other authors

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