With the rapid growth of technologies such as the Internet of Things (IoT) and artificial intelligence (AI) in recent years, giant data transmission and processing capacities of computers have faced major hurdles (1, 2). At the moment, memory is the key bottleneck in computer processing big data processes. The CPU and the memory are distinct in the standard Von Neumann design, while frequent data exchange uses a lot of energy, resulting in the "Memory Wall" problem (3). On-chip cache, being the crucial constituent of CPU, accounts for a pivoltal portion of the system's overall power consumption. If the power wastage of the on-chip cache could be lowered, the ultimate performance of the CPU can be strengthened. The typical SRAM-based cache is vulnerable to high static leakage power consumption, and scaling up its capacity is challenging. Magnetic random access memory (MRAM) (4), as a new non-volatile storage technology, is expected to break the limitation at the cache level (5).
In the paper, MRAM cache is used to limit static leakage power consumption. A quad-core CPU MRAM hierarchical cache system is established in the designed MRAM cache, with the high-speed Spin-Orbit-Torque (SOT)-MRAM (6) functioning as the L1 cache and the high-density Spin-Transfer-Torque(STT)-MRAM (7) serving as the L2 shared cache. A non-inclusive allocation method is adopted for the data-exchange strategy, by which the number of the write operation in the L2 STT-MRAM cache is reduced, and the energy consumption of the system is further reduced. The designed system is simulated and verified based on gem5 (8) software framework. The simulation results show that strategy of the hybrid MRAM memory is a promising candidate for high-speed and low-power on-chip cache. 

**References:** 
(1) Y. Li, Z. Wang, R. Midya et al., Journal of Physics D: Applied Physics., vol. 51, p.503002(2018) 
(2) J.-M. Hung, X. Li, J. Wu et al., IEEE Transactions on Electron Devices., vol. 67, p.1444-1453(2020) 
(3) X. Huang, C. Liu, Y.-G. Jiang et al., Chinese Physics B., vol. 29, p.078504(2020) 
(4) M. Durlam, P. J. Naji, A. Omair et al., IEEE Journal of Solid-State Circuits., vol. 38, p.769-773(2003) 
(5) F. Oboril, R. Bishnoi, M. Ebrahimi et al., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., vol. 34, p.367-380(2015) 
(6) K. Jabeur, L. D. Buda-Prejbeanu, G. Prenat et al., International Journal of Electronics Science and Engineering., vol. 7, p.501–507(2013) 
(7) D. Apalkov, A. Khvalkovskiy, S. Watts et al., ACM Journal on Emerging Technologies in Computing Systems., vol. 9, p.13:1–13:35, (2013) 
(8) N. Binkert, B. Beckmann, G. Black et al., ACM SIGARCH computer architecture news., vol. 39, p.1-7(2011) 

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/e6c3464562793d32243ffed0b7022f0e.png)

Hierarchical Cache Configuration Based on Hybrid SOT and STT

As a promising non-volatile memory, Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) suffers from high error rate due to stochastic switch [1]. Some papers use Error Correcting Code (ECC) with powerful error correction capabilities to suppress high error rate, which lead to high delays and high check bit consumption. According to published reports, the error occurring of STT-MRAM is a serious asymmetry phenomenon [2]. The write error rate of 0 → 1 is much higher than that of 1 → 0 since 0 → 1 transition requires higher energy to ensure reliably commute the value. The traditional ECC approaches for other kinds of memories are designed for symmetric error correcting, which are not suitable for STT-MRAM. A weighted error correction mechanism is proposed and fulfilled in the paper, which can be used for the asymmetric error situation. Firstly, the codewords are weighed by estimating the different probabilities of error in state 0 and 1. In STT-MRAM, the error occurrence rate on state 0 is much higher than that on state 1. Through the check matrix, the words can be preliminarily judged to determine which bits may be wrong. Through the different weights of data 0 and 1, a bit with the highest error probability can be calculated. Then this bit is flipped to get a new codeword, which is substituted into the check matrix again to get a new error situation. The process of WECC is shown in Fig.1. If situation improves, the new codeword can be kept. Otherwise, the previous substitution operation is cancelled. In order to ensure the effectiveness of the error correction mechanism, the assistance of other ECCs such as BCH or LDPC is usually required. The error correction mechanism proposed in the paper can effectively reduce the error correction delay and decrease the check bit consumption. A virtual system in GEM5 is built up to evaluate the proposed WECC mechanism. The simulation results are used for the analysis of the error correction algorithm, showing the effectiveness of the WECC proposed in the paper for STT-MRAM.

![](https://assets.underline.io/uploads/markdown_image/1/image/fa6a1883b97a9ef7b919f61da0895f72.jpg)

Fig.1 Process of WECC

Weighted Error Correcting Code (WECC) against Asymmetric Error of STT-MRAM

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**Session Co-Chairs:** Shouzhong Peng, *Beihang University* and Luding Wang, *Eindhoven University of Technology*

DPA: Spintronic Devices for Memory and Computing

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GPD - MRAM, Magnetic Logic and Related Devices III

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Qiguang Wang

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Hierarchical Cache Configuration Based on Hybrid SOT and STT

Weighted Error Correcting Code (WECC) against Asymmetric Error of STT-MRAM

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