A multiscale TCAD model is introduced in the presentation to investigate the intrinsic physical properties of type-II DHBTs. The simulation environment is composed of a two-dimensional hydrodynamic model and an one-dimensional full-band atomistic quantum transport solver. After careful calibration, good agreements between simulations and experiments have been obtained in both the DC and AC characteristics. Moreover, the transport properties of the device have been investigated in the ballistic and dissipative case. Last but not least, the performance of agreesively down-scaled transistors has been simulated to shed light on the realization of transistors towards and beyond 1 THz.

Multi-Scale Modeling of Type-II DHBTs: from Bandstructure to Self-Heating Effects

**Monday, September 22nd**

**Session Chairs:** Cristell Maneux *IMS Bordeaux* and Virginie Nodjiadjim *III-V Lab*

Today, the ever growing communication services such as remote work, e-learning, e-healthcare and intensification of social relations supported by massive data transmission, give a new impulse to further investigate various methods to increase transmission network capacities with Tb/s/channel objective. This workshop will give insights into different key aspects of the device-to-circuit value chain highlighting the need for devices combining very high symbol rate multi-level signal generation with large output swing to efficiently drive electro-optical (E/O) modulators.

A variety of novel (i) InP DHBT devices –both InGaAs and Sb types-, (ii) calibration and measurement approaches, (iii) physics-based device simulation coupled methods including compact model and (iv) state-of-the-art E/O modulator results are covered in this workshop.
The consistency of the whole value chain leads, for instance, to very-high-symbol-rate PAM (or QAM) modulation formats.

**This session has 10 lectures. If you don't see them all please click on the 'SEE ALL' button located in the top right corner of the page**

13. From InP bipolar transistors to analog front-end integrated circuits: Innovations in devices, THz measurements, compact modeling and circuits

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Xin Wen

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Multi-Scale Modeling of Type-II DHBTs: from Bandstructure to Self-Heating Effects

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