Advances in process and fabrication enable the relentless downscaling into the nanometer regime and open the way to a new era of device structures and materials. Approaching the atomic scale, individual imperfections such as point defects, which are inevitably present in bulk and interface systems, and their distributed properties start to become a decisive factor for device reliability and start to dominate the device performance. Keeping pace with the technological progress on the theoretical simulation side, hence, requires reliable approaches based on fundamental physics such as ab initio calculations. Largely driven by the beat of Moore’s law itself and the increase of computational resources, atomistic first-principles calculations are routinely used nowadays to predict structural and electronic properties. Nevertheless, understanding the underlying model together with a careful analysis of the results is essential to draw meaningful conclusions. Particularly in the field of device reliability, these advancements have enabled an improved understanding of intrinsic and extrinsic point defects in various materials such as Si/SiO2/HfO2 or SiC/SiO2 stacks. Due to the predictive power and accuracy of density-functional-based calculations characteristic defect properties such as thermodynamic and optical transition levels as well as their interaction with the surrounding can be directly connected to experimental observations. Hence, it is possible to assess how vacancy, interstitial, antisite, substitutional, and other defect types impact and perturb the device performance. Moreover, these results provide vital input for the development of modern predictive TCAD models.

Modeling of Bulk and Interface Defects for Reliability Prediction on the Atomistic Scale.

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9255.pdf

**Abstract:**

Silicon and its native oxide SiO 2 are the most commonly used materials in semiconductor device technology. After decades of research in this field, details of the initial oxidation and the subsequent O migration and amorphization are still a subject of interest. In this paper, we present a multiscale modeling approach to investigate the oxidation process of a Si(100) surface. Starting from the adsorption and dissociation of single O 2 molecules, we further extended our investigations towards the initial oxidation of the first Si layer and subse- quent O migration. Finally, we construct a realistic model of a Si/SiO 2 interface consisting of around 5000 atoms. The employed simulation techniques used in this study range from density functional theory (DFT) to density functional based tight binding (DFTB) to classical molecular dynamics (MD).

Multiscale Modeling Study of Native Oxide Growth on a Si(100) Surface

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9152.pdf

**Abstract:**

A ML based framework is presented to predict the formation and structure of defect in amorphous structures, aiming at reducing the computational costs which these studies require. The framework is applied to the prediction of hydroxyl E\' center defects in amorphous silicon dioxide. The results demonstrate a competitive level of accuracy, while being computationally inexpensive, when compared to DFT.

Machine Learning Prediction of Defect Structures in Amorphous Silicon Dioxide

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9266.pdf

**Abstract:**

It is well established that oxide defects are a major threat concerning the reliability of electronic devices. Point defects like the oxygen vacancy and hydrogen related defects like the hydrogen bridge and the hydroxyl-E\' center can trap charges from the Si substrate during operation. Here we present a statistical study of parameters by analyzing 144 defects of each type in amorphous SiO2 . We use density functional theory in conjunction with a hybrid functional to provide a large and accurate dataset of defect parameters such as the relaxation energy or the charge transition level and link them to bias temperature instability in nMOSFET devices.

Statistical Ab Initio Analysis of Electron Trapping Oxide Defects in the Si/SiO2 Network

We extend our framework for hot-carrier degradation (HCD) modeling by covering the impact of self-heating (SH), which has three main aspects: (i) perturbation of carrier transport, (ii) acceleration of the thermal contribution to bond breakage, and (iii) and shortening vibrational lifetime of the bond, i.e. reducing the multiple-carrier mechanism rate. We validate the framework against HCD data acquired in nFinFETs and pNWFETs under various stress conditions, analyze the importance of each of the aforementioned aspects, and explain why in n-channel FETs SH slightly inhibits HCD, while in p-channel devices HCD is accelerated by SH.

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-channel Transistors

**Monday, September 20th**

**Session Chairs**: Philippe Blaise *Silvaco* and Denis Rideau *STMicroelectronics*

This tutorial will introduce to atomistic methods such as Density Functional Theory (DFT), Molecular Dynamics (MD) and Non-Equilibrium Green's Functions (NEGF). Novel simulation techniques to determine atomistic details of bulk and device properties will be address, with special emphasis on applications to materials for nano/opto electronics. The tutorial will explore the potentialities of atomistic methods in predicting the physics of these new materials and structures, including defects and their electrical and optical properties, but will also discuss how to bridge the results of simulations with experiments and spectroscopic signatures.

4. Atomistic simulations supporting new materials & process developments

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

ESSCIRC ESSDERC Educational Events

The Educational Events of ESSCIRC ESSDERC 2021. 

**Session Chairs:** Zlatan Stanojevic, Global TCAD Solutions; Denis Rideau, STMicroelectronics

D2L-5: Simulation & Modeling of Defects & Traps

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





6A -TX (Transistors)

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

IRPS 2022 Main Conference 

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Markus Jech

5

11

SHORT BIO

Presentations

Modeling of Bulk and Interface Defects for Reliability Prediction on the Atomistic Scale.

Multiscale Modeling Study of Native Oxide Growth on a Si(100) Surface

Machine Learning Prediction of Defect Structures in Amorphous Silicon Dioxide

Statistical Ab Initio Analysis of Electron Trapping Oxide Defects in the Si/SiO2 Network

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-channel Transistors

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES