Chenming Zhang was born in Yongqing, Hebei Province, China in 1988. From 2006 to 2007, he studied at Tongji University, Shanghai, China. He received the Bachelor of Science degree (cum laude) in Electronic Engineering from Politecnico di Torino, Turin, Italy, in 2010, and the Master of Science degree in Electrical Engineering and Information Technology from ETH Zurich, Zurich, Switzerland, in 2013. Since 2013, he started to pursue his PhD's degree in the integrated circuits group (named mixed-signal microelectronics group at that time) at Eindhoven University of Technology, Eindhoven, The Netherlands. His PhD project is on broadband continuous-time MASH Sigma-Delta ADCs.

In 2010, he was with National Institute of Metrological Research, Turin, Italy, as an intern. From 2011 to 2012, he was with the ABB Switzerland Ltd., Semiconductors, Lenzburg, Switzerland, as an intern. Since 2018, he has been working as a wideband ADC designer in the group "Radar & Wideband Frontends", business line Radio Frequency Processing, NXP Semiconductors, Eindhoven, The Netherlands. His current research interests include high-speed broadband high-linearity continuous-time Sigma-Delta ADC design and ADC calibration techniques.