**Please read the paper on the following link:**

https://1worldcontent.com/ess/9263.pdf

**Abstract:**

This paper presents a dual-mode, multi-bit, second-order oversampling ADC, which can be configured into Sigma-Delta (SD) mode or Incremental (I) mode for interfacing a single or multiple sensors in multi-sensor platforms for automotive applications. Implemented in a 130-nm CMOS technology, the proposed ADC uses only 0.4µm devices and operates at 2.5-V supply in order to be connected to high-voltage sensors, at the cost of intrinsic lower efficiency. The device achieves a maximum SNDR of 63.0 dB and 56.4 dB in the two modes, respectively, with a bandwidth of 2.1 MHz. By reducing the bandwidth to 1.25 MHz in SD-mode a SNR of 73.2 dB is achieved. In both operating modes, the ADC is clocked at 80 MHz, consuming 2.6 mA.

A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9190.pdf

**Abstract:**

This paper presents the design and the validation of a continuous-time 2nd-order analog filter with 40 MHz -3 dB cut-off frequency. The circuit synthesizes a pair of conjugated complex poles by leveraging the inductive behaviour of the source node of the folded branch of a differential amplifier. This circuital technique dominates noise power and harmonic distortion by a simple input MOS transistor pair of a differential stage, resulting in 7-nV/√Hz in-band Input Referred Noise power spectral density and 69 dB output Dynamic Range. Moreover, this solution enables the introduction of gain in the filter, relaxing gain, power, and bandwidth requirements of the following stages in cascade structure. A filter prototype is realized in 28 nm CMOS, consuming 309 µW from 1.1 V and performing –6 dBm in-band Input IP3 at 20 dB passband gain.

309-µW 40-MHz 20-dB-Gain Analog Filter in 28nm-CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9137.pdf

**Abstract:**

This study presents the first in depth characterization of deep cryogenic electrical behavior of a commercial 16nm CMOS FinFET technology. This technology is well suited for a broad range of applications, including quantum computing, quantum sensing, and quantum communications. Cryogenic DC measurements and physical parameters extraction were carried out on this commercial FinFET technology, operating at room temperature, i.e., 300 K, and down to 2.95K for different device types and geometries. This represents the main step towards cryogenic compact modeling and optimization of three-dimensional CMOS structures for quantum computations.

Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing

**Session Chairs:** Georges Gielen, Katholieke Universiteit Leuven; Venkatesh Srinivasan, Texas Instruments

B2L-3: Oversampled ADC

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
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Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Session Chairs:** Viola Schaffer, Texas Instruments; Makoto Nagata, Kobe University

D1L-6: Analog Techniques

**Session Chairs:** Louis Hutin, CEA-Leti; Claudio Bruschini, École Polytechnique Fédérale de Lausanne

Andrea Baschirotto

3

23

Presentations

A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter

309-µW 40-MHz 20-dB-Gain Analog Filter in 28nm-CMOS

Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing

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