When it comes to modelling materials of technological interest for microelectronics and their properties, the challenge is great, especially when considering current low-temperature processes, 3D architectures for the integration of ultra-thin, nanostructured materials with controlled performance. The continuum methods on which TCAD simulation in industrial environments typically relies are inherently unable to capture the resulting effects at these scales such as defect formation and growth mechanisms. 
In this talk, we will see how it has become necessary to implement a series of atomistic tools at different time and size scales to capture all the effects necessary for reliable process prediction. A review of atomistic methods will be proposed from the most conventional methods such as molecular dynamics and DFT to state-of-the-art methods such as going “beyond DFT” and Machine Learning potential. Examples on manufacturing process and defects characterization will be given.
Finally, one the main purpose of these studies is to help microelectronics engineers. Example of implementation of atomistic data into industrial TCAD tools will be given and discussed.

What multi-level strategy for modelling processes and defects in semiconductors at the atomic scale? Current approaches, necessary developments and new needs.

Advances in process and fabrication enable the relentless downscaling into the nanometer regime and open the way to a new era of device structures and materials. Approaching the atomic scale, individual imperfections such as point defects, which are inevitably present in bulk and interface systems, and their distributed properties start to become a decisive factor for device reliability and start to dominate the device performance. Keeping pace with the technological progress on the theoretical simulation side, hence, requires reliable approaches based on fundamental physics such as ab initio calculations. Largely driven by the beat of Moore’s law itself and the increase of computational resources, atomistic first-principles calculations are routinely used nowadays to predict structural and electronic properties. Nevertheless, understanding the underlying model together with a careful analysis of the results is essential to draw meaningful conclusions. Particularly in the field of device reliability, these advancements have enabled an improved understanding of intrinsic and extrinsic point defects in various materials such as Si/SiO2/HfO2 or SiC/SiO2 stacks. Due to the predictive power and accuracy of density-functional-based calculations characteristic defect properties such as thermodynamic and optical transition levels as well as their interaction with the surrounding can be directly connected to experimental observations. Hence, it is possible to assess how vacancy, interstitial, antisite, substitutional, and other defect types impact and perturb the device performance. Moreover, these results provide vital input for the development of modern predictive TCAD models.

Modeling of Bulk and Interface Defects for Reliability Prediction on the Atomistic Scale.

The current electronic device scaling is reduced to 5 nm and smaller technology nodes based on EUV lithography, it is expected to reach sub-nm technology node within a decade. Along with the EUV scaling, the space of medium/upper level BEOL provides both challenges and opportunities to device research community. Rational design of device materials using atomic scaling modeling methods can contribute the accelerated development of the new technology materials based on fundamental understanding on their atomic and electronic scale properties. Using the density functional theory (DFT), atomistic kinetic Monte Carlo (KMC) and time-dependent DFT (TDDFT) simulations methods, we have been investigating the BEOL process compatible oxide semiconductors for monolithic 3 dimensional (M3D) integration of functional devices in the intermediate interconnect layers. In this tutorial, we will discuss about the multiscale modeling approaches applied to device materials modeling for n- and p-type oxide semiconductor design for BEOL applications. We will examine atomic and electronic structures of both n-type and p-type oxide semiconductors in crystalline and amorphous phases. Using the rational design approach to oxide semiconductors based on DFT calculations, we are exploring the complex oxide material parameter space and charting possible pathways to develop both p-type and n-type oxide semiconductor candidates for BEOL CMOS applications. We will discuss the design rationales of currently identified oxide semiconductor candidates (Ta2SnO6, TiSnO3 for p-type In-W-O system for n-type) and validation experiments to accelerate the focused development of BEOL oxide semiconductors with superior performance. These oxide semiconductors will provide case study examples of the materials deign method applied to electronic device materials in this tutorial. 
This work was supported by ASCENT, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

Rational Design of BEOL Oxide Semiconductors for Emerging Device Applications.

It is well known that, over a wide range of wavelengths, a graphene sheet absorbs 2.3% of the light passing through it. This value is directly related to the fine structure constant, which can be interpreted by the very particular band structure of this material. Remarkably, it has been shown experimentally that thin InAs films exhibit an aborption spectrum characterized by steps that can also be related to the fine structure constant. We present numerical simulations (TB, KP) showing that this phenomenon is very robust and is obtained for a very large number of semiconductor materials. We complement this work with analytical calculations to understand the physical origin of this behavior. The comparison with graphene is discussed.

Optical absorption quantization in nanolayers of semiconductors

Halide perovskite semiconductors, either fully inorganic or hybrid organic-inorganic, have attracted a lot of interest since 2012 owing to their excellent performances for photovoltaic applications. These low-cost semiconductors have attractive intrinsic physical properties for optoelectronics, including direct band gaps, small effective masses, large carrier mobilities, sizeable optical absorption and quantum yield for luminescence. Available tools, including commercial codes, for semiconductor device simulations provide reasonable descriptions of the perovskite device characteristics under operation. However such simulations are still hardly predictive. The aim of the presentation will be to give an overview of the current challenges for such simulations by comparison to classical semiconductors, including 1) the diversity of compositions, nanostructure dimensionalities, crystallographic structures or processing of the perovskite materials, 2) the unusual physical properties of this new class of soft and ionic semiconductors, 3) the primary importance and complexity of the interfaces in perovskite-based thin film heterostructures

Perovskite semiconductors: current challenges for predictive atomistic and device simulation.

Computer simulations are well established to support experimental R&D in OLED and OPV technology: On the molecular scale, quantum chemistry tools such as DFT are used to compute molecular properties such as HOMO or levels or excitation energies, while continuum models, e.g. drift diffusion, are efficient tools for virtual design on the device level. 
However, the application of quantum chemistry methods is limited to a few molecules at best, prohibiting the direct computation of material properties in thin films and their impact on device performance. Continuum models on the other hand rely on parametric models which often need to be calibrated with experiments due to the lack of predictive microscopic models. 
We bridge this gap of scales using a multiscale workflow that connects fundamental chemistry and device design: Using a physical vapor deposition protocol with customized force-fields and a quantum embedding scheme we generate digital twins of OLED layers and devices. For these digital twins we compute electrical properties such as electron affinity, ionization potential and permittivity. Using a kinetic Monte-Carlo protocol we conduct virtual experiments on the digital twins to simulate charge carrier and exciton dynamics in OLED devices to e.g. compute charge carrier mobility or device efficiency. These microscopic simulations generate a fundamental understanding on how molecular properties trigger and balance microscopic processes, thereby enabling materials and device designers to systematically eliminate bottlenecks in OLED performance. Further, the multiscale workflow can be used to parametrize continuum models from first principles, facilitating full virtual design.

Connecting quantum chemistry and device level simulations via multiscale simulation workflows

This tutorial will focus on how to determine the dielectric, electronic transport, and magnetic properties of two-dimensional (2D) materials from first principles using density functional theory (DFT). We will exhibit a simple yet robust methodology to extract the dielectric constant of a monolayer/few-layer structures from a DFT calculation. We will illustrate the dielectric constant methodology by determining the low- and high-frequency dielectric constant of hexagonal boron-nitride, transition metal dichalcogenides (TMDs), and novel unexplored dielectrics. Next, we will show how our open-source Plane-wave Electron TRAnsport (PETRA) quantum transport code can be used to simulate transport in nanowires and nanoribbons. Finally, we will show how from DFT calculations for various magnetic configurations, the exchange interaction can be described as a function of concentration. Once the exchange interaction description is determined, Monte Carlo simulations can be performed to determine the magnetic order and the Curie/Néel temperature, the magnetic properties of layered materials can be determined. We will illustrate the approach using monolayer MoSe2 and show that five different magnetic orderings in 2D materials are revealed.

Computing Dielectric, Electronic Transport, and Magnetic Properties of Two-Dimensional Materials from First Principles

Mixed signal circuits are at the core of the IoT where the main sales
argument for devices is their capability to interact with the environment through
multiple sensors and actuators. Unfortunately, mixed signal integrated circuits,
unlike digital circuits, do not scale according to Moore’s law. The 3D-MUSE
project investigates emerging monolithic/sequential integration technology that
integrates CMOS tiers of different technology nodes to tackle this scaling challenge.
This technology offers 3D inter-tier connection densities on par with
horizontal in-tier CMOS interconnection densities, thus allowing transistor level
placement of circuit components across tiers at minimal to no area overhead cost.
Mixed signal functional circuit blocks can thus be implemented in a volume and
combine device options from different CMOS technology nodes to maximum advantage, e.g. reducing parasitics, area, cost and power, and gaining processing
speed. The 3D-MUSE project combines efforts from 3D technology developers
and ASIC design groups to showcase examples of such mixed-signal systems,
enabling smart sensor interfaces implemented as ’systems-in-cube’.

Introduction: The 3D-MUSE project

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performanc

3D sequential integration: opportunities and challenges

Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process1,2. Suitable for 3D stacking based on TSV or Hybrid Bonding technologies because of the low granularity of these 3D interconnect elements, this methodology becomes more difficult to apply to 3D sequential technologies once trying to integrate Monolithic Inter-tier Vias (MIV) with higher density (around 1.108 vias per mm2). In this paper, we describe a methodology to create a unified design environment, which includes several technologies attached to different tiers. Main advantage of this methodology is that designing a 3D circuit may no more require several design environments, thus simplifying simulations, verifications and layout finishing.

Merging PDKs to build a multi-process multi-tier 3D design environment

A 14-bits cyclic ADC is implemented in two-tier 3D sequential integration
(3DSI) multi-process technology. The ADC specifications are intended
for the daughter-payloads of the investigation of cusp irregularities (ICI) sounding
rocket series, i.e. small sensor platforms that are ejected in-flight to measure
plasma electron density in a cloud around the rocket. The two 3DSI processes
used are a 65nm SOI technology with 28nm shrink transistors in the top tier
and 28nm FDSOI as the bottom tier. This work aims to explore architectures
in a high-density interconnect 3D sequential integration process for area and
power reduction, exploiting fine-grained transistor placement as well as device
parameter optimization having the choice of two different CMOS technologies
for each individual device.

14-bits Cyclic ADC in 3D sequential multi-process Technology

This presentations deals with innovative approaches of 3D stacking Image sensors. Comparisons with conventionnal 3D vs sequential stacking is described.

Underline digital video library

What multi-level strategy for modelling processes and defects in semiconductors at the atomic scale? Current approaches, necessary developments and new needs.

Modeling of Bulk and Interface Defects for Reliability Prediction on the Atomistic Scale.

Rational Design of BEOL Oxide Semiconductors for Emerging Device Applications.

Optical absorption quantization in nanolayers of semiconductors

Perovskite semiconductors: current challenges for predictive atomistic and device simulation.

Connecting quantum chemistry and device level simulations via multiscale simulation workflows

Computing Dielectric, Electronic Transport, and Magnetic Properties of Two-Dimensional Materials from First Principles

Introduction: The 3D-MUSE project

3D sequential integration: opportunities and challenges

Merging PDKs to build a multi-process multi-tier 3D design environment

14-bits Cyclic ADC in 3D sequential multi-process Technology

Innovative Fine Pitch Architectures dedicated to Image Sensors: from Hybrid Bonding to 3D Sequential integration

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES