The design and discovery of new functional materials has acquired a sense of urgency recently for critical-elements reasons. In the case of permanent magnets, computational and experimental methods are being used synergistically to aid the search for new materials with large values of saturation magnetization Ms, anisotropy K, and Curie temperature Tc [1-3]. Ideally, the materials exhibit μoMs &gt; 0.8 T and K &gt; 1.5 MJ/m3. Another criterion for the evaluation of new permanent-magnet materials before the typically difficult task of synthesis and coercivity development is the hardness parameter κ = (K/μoMs2)1/2 [3]. This parameter can also be written as κ = (Ha/2Ms)1/2, where Ha = 2K/μoMs is the anisotropy field, so that each value of κ yields a straight line when Ha is plotted vs. Ms. Ideally, κ is comparable to or larger than one [3, 4]. Figure 1(a) combines the Ms and κ requirements to yield an area of promising permanent magnets (yellow). However, the main figure of merit in permanent magnets energy product. Figure 1(b) plots K against Ms, which has several advantages: (i) the blue isoenergetic curves show the expected maximum energy product, (ii) real-structure factors such a remanence ratio, Kronmüller factor α, packing fraction, and loop shape easily be included in the isoenergetic curves; and (iii) the primary intrinsic properties are K and Ms, not Ha and Ms. If the boundary of the yellow area and blue curves were physically equivalent, the boundary and the blue curves would be approximately parallel. This in not the case for the ascending branch of the boundary, where the curves are almost perpendicular due to the very different natures of hardness and energy product. Aside from helping to identify promising permanent-magnet materials, this work underlines the long-term aspect of permanent-magnet development. The work in Nebraska is supported by NSF-DMREF (No. 1729288), NSF-EQUATE (OIA-2044049), the NU Collaborative Initiative, and NCMN, whereas the research at Ames is funded by DOE.

![](https://assets.underline.io/uploads/markdown_image/1/image/115daa171706731e49904daa3478c12a.jpg)

Fig. 1. Permanent-magnet performance plots: (a) Ha-Ms plot and (b) K-Ms plot, the axes showing μoH and μoM. The specific model used for the blue curves assume Mr = Ms, a straight M(H) line in the second quarter, and α = 0.4.

Criteria for Permanent-Magnet Materials

The application of gate voltages in ferromagnet/Oxide/Heavy metal thin film multilayer has been identified as one possible candidate to manipulate their anisotropy at will [3], [1], [4]. Unfortunately, this method has proven to be unreliable in terms of the reversibility: e.g, the application of a gate voltage onMgO/CoFeB/Ta [3] causes an irreversible change of the magnetic anisotropy axis from in plane to out-of-plane, while HfO2/CoFeB/Ta stacks display a more complicated behavior, with different regimes characterized by different reversibility behaviors [2]. The microscopic origin of these phenomena remains unclear and is the object of our inquiry. In this work we performed ab-initio simulations on 6 setups comprising Fe/O, HfO2/Fe, MgO/Fe interfaces each one with frontal and interstitial oxygen atomic configurations (fig.1). The pure Fe/O interface prefers interstitial oxygen configurations while the addition of oxides seems to switch this trend around. In particular, HfO2/Fe displays a strong preference for the frontal oxygen arrangement, leading us to identify a possible hypothesis for the phenomenon of the multiple magneto-ionic regimes displayed. In it’s as grown form, HfO2/CoFeB is characterized by an underoxidized ferromagnet interface [2]. The application of a gate voltage on HfO2/CoFeB pushes some of the oxygen species in proximity of the interface where they occupy the stable frontal site. Further application of a gate voltage pushes other oxygen atoms toward the still free and more unstable interstitial sites. The occupation of these interstitial sites has the effect of destroying perpendicular magnetic anisotropy as seen both in experiments and simulations [5] [1]. Once these more mobile interstitial sites are occupied, magnetic anisotropy can be switched reversibly by inverting the gate voltage and adjusting the interstitial site occupation (fig.2)

![](https://assets.underline.io/uploads/markdown_image/1/image/40c593503d5a4f3ee9c27db4ad2dc04d.jpg)

Comparison of the different interfacial configurations in the differentsamples. The bar plots represent the ground state energies and highlight themore stable configuration

![](https://assets.underline.io/uploads/markdown_image/1/image/f5dc5807d0f4552079d7a39375420a9e.jpg)

Hypothesis for the mechanism governing magneto-ionic regimes inHfO2/FM stacks. The text highlights the magnetic properties of the interface under different oxidation conditions.

Reversible anisotropy manipulation via gate voltages in ferromagnet/oxide multilayers

The motion of domain walls by the use of the magnetic fields as well as spin polarized currents has been a major part of spintronics in the last two decades. The two mechanisms of current induced domain wall motion are Spin transfer torque(STT) and Spin orbit torques(SOT). In the recent years, compensated ferrimagnets have been in focus due to their ability to reach the magnetic and the angular momentum compensation points. At the angular mometum compensation point the precessional motion of the local magnetic moment becomes negligible which has shown to have massively increase the domain wall velocity[1,2]. Here we will focus on a rare-earth free ferrimagentic nitride called Manganese Nitride (Mn4N). We have previously shown epitaxially grown Mn4N has a very low magnetization (71 kA/m) and a very high perpedicular magnetic anisotropy (PMA) with mm sized domains[3]. This low magnetization is due to the two different Mn sub-lattices in the anti-perovskite crystal structure. With such a small magnetization and a high spin polarization led us to obtain a very high domain wall velocity of more than 900m/s at J=1.3*1012 A/m2 using pure STT[4]. In this work, we have have shown an even larger domain wall velocity approaching 3000 m/s at J=1.26*1012 A/m2 using pure STT near the magnetic and the angular compensation points in epitaxially grown Ni doped Mn4N[5]. The magnetic and angular momentum compensation points are obtained by the adjustment of Ni doping in this system at room temperature. These high domain wall velocities are comparable to the best velocities obtained by SOT. Also, in this system there is no requirement for an external in-plane field as shown in some other systems by SOT. Moreover, we also demonstrate a reversal of the domian wall motion direction after crossing the compensation points where the domain walls move in the same direction as the flow of electrons. This phenomenon will be explained with the help of ab-initio calculations.

![](https://assets.underline.io/uploads/markdown_image/1/image/c0c2ec29f2ef977b88dd4a5f908583e9.jpg)

Current density vs Velocity curves for Mn4-xNixN thin films. Filled symbols show samples before and the open symbols after the compensation point.


![](https://assets.underline.io/uploads/markdown_image/1/image/b73b2f498d533d34f95601fada6e88b3.jpg)

MS vs Velocity plot, measured for J=1*1012 A/m2(blacksquares) is compared with the best fit obtained using the q−φmodel.

Current driven domain wall dynamics across the angular momentum compensation point in epitaxially grown ferrimagnetic Ni-doped Mn4N thin films

This paper presents a method that extracts junction temperature of SiC MOSFETs by measuring a unique turn-on delay. In preceding work, the turn-on delay was identified as a particularly promising temperature-sensitive electrical parameter for SiC MOSFETs. The reasons for this are its simple calibration, its insensitivity to the device current, its linear temperature dependency as well as the particular behavior of the charge carrier mobility of SiC. However, state-of-the-art extraction circuits for turn-on delay only work with a limited time resolution. Thus, they can only be applied to slowly switched SiC MOSFETs. This work proposes a circuit for turn-on delay extraction with a time-to-digital converter that allows the time resolution to be significantly increased. Thereby, the circuitry allows utilizing turn-on delay as an effective temperature-sensitive electrical parameter for junction temperature extraction of SiC MOSFET operated with fast switching transients. The feasibility of the approach is experimentally validated in this work with a developed extraction circuit using a SiC MOSFET power module as a device under test.

Online Junction-Temperature Extraction Method for SiC MOSFETs Utilizing Turn-on Delay

Trivalent europium ions (Eu(III)) exhibit high color purity, but their absorption coefficients are very small. Eu(III) complexes that utilize energy transfer from antenna ligands to a metal center have been developed to produce efficient luminescent materials. Nevertheless, their energy transfer mechanisms, which depend on the kinds of ligands and their configurations, are still elusive due to weak and complicated interactions between organic ligands and lanthanide ions. To elucidate the energy transfer mechanisms, we measured the temporal changes of emission and absorption spectra using time-resolved photoluminescence (TR-PL) and transient absorption (TA), respectively. We compared the intramolecular energy transfer of the mononuclear complex and the dinuclear complex. Although they have identical antenna chromophores, the dynamics of the two complexes are different. The lifetime of the ligand S1 state in the dinuclear complex is faster than in the mononuclear complex. By comparing molecular geometries between the complexes, we concluded that this difference originated from the difference in the relative configuration of the two triphenylenes. Our discovery helps to establish the design strategy of highly efficient luminescent lanthanide complexes in photofunctional materials.

Energy transfer dynamics in luminescent Eu(III) complexes with phosphine oxide ligands

5G and Beyond 5G applications are driving research towards highly integrated PA modules with multiband capabilities. Multiband requirements, along with the need for reduced power consumption, make the PA design highly critical since high PAPR signals require the PA to be backed-off from its peak power in order to achieve the necessary system linearity. This calls for an important shift from traditional PA design to more advanced PA architectures capable of handling signals with high PAPR while maintaining high efficiency and linearity on a broad frequency range. In addition, achieving high performance and reliability while maintaining compact size requires innovative thermal and electromagnetic management schemes. In this talk, I will give an overview of the challenges, recent progress and trends related to the integration of high efficiency PA design in RF-SOI technology for mobile applications operating below 6GHz.

High-Efficiency Power Amplifiers in RF-SOI technology: Challenges, Progress and Perspectives

Recent advancements and applications in compact phased arrays, MIMO basestations and handsets, automotive radar, etc. are driving the need for RF power generation in CMOS technologies to accomodate high complexity systems that require RF output power. This presentation will provide an overview of CMOS device concepts up to architectural choices that have been proposed to improve RF power and efficiency in CMOS technologies. This discussion focuses on RF power amplifier concepts.

Overview of RF Power Generation Using CMOS Technologies

This work presents an in-package D-band wireless module co-integrating an innovative channel-bonding transmitter IC in 45 nm CMOS PDSOI technology and a patch antenna fabricated using a low-cost printed circuit board process. The transmitter is composed of two up-conversion chains with dedicated millimeter-wave local oscillator generators and operates over contiguous sub-bands around 147.96 GHz. The two sub-band signals are combined off-chip using a substrate integrated waveguide diplexer and radiated by a four-patch antenna array realized on the same laminate substrate. The total output band spans from 139.3 to 156.6 GHz. A data rate of 84.48 Gb/s is demonstrated using 64-QAM.

D-band on GF 45RFSOI

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we will review the development of partially depleted 200 mm & 300 mm RF SOI technologies developed at STMicroelectronics to address 5G Front End Module (mainly RF switches and Low Noise Amplifiers) and new requirements implied by 6G enablement.

Advanced 200 mm and 300 mm RF SOI Technologies Targeting 5G and beyond (6G) RF Front End Module SOC

Performances of RF and millimeter-wave integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future low power wireless communication systems operating in the millimeter-wave range. Innovation pathways of the FD SOI technology to fulfill the requirements of millimeter-wave wireless systems will be discussed, i.e. channel engineering or metal gate at the transistor level, and smart PN junction implants combined with high-resistivity Si base or the silicon porosification at the substrate level. The importance of a powerful simulation tool to save silicon runs, and thus time and cost, will be highlighted.

Next generation of FD SOI platform to fulfill the requirements of millimeter-wave wireless systems

The research area of improving the performance, cost, and size of RF solutions for 5G LTE is very active with many developments which shapes the semiconductor industry evolution. Mobile cellular subscribers are expected to reach more than 6.5 billion by 2021 and 5G LTE will bring high data capacity as well as low latency using sub-6GHz and mm-Wave spectrum. The short course presents the status of 5G LTE RF Front End (RFFE) techniques to deliver an over gigabit-per-second data rate such as Carrier Aggregation, MIMO as well Wider Modulation Bandwidth for LTE and mm-Wave spectrum. 
The RFFEs will integrate power amplifiers, switches, couplers, tuners, and active acoustic filters. The workshop will cover practical design aspects for 5G FEMS with emphasis for FEM architectures, power amplifiers, switches, and active filters as well the technologies involved into these designs. The workshop will also cover aspects of new 5G LTE integration for envelope tracking and LNA design. 5G LTE New Radio (NR) will increase the complexity for RFFEs and will be covered in this workshop .



Next gen 5G RF Front End challenges

Demand for better wireless signals has increased with larger networks and connected devices. Wi-Fi has also increased in speed, allowing more connections through improvements in frequency used and data transmission. The enhancements for Wi-Fi 6 impose new design challenges. One of the requirements is on the amplifier section where higher linearity and a flatter response curve is necessary. Accomplishing this requires better designed RF components. Another challenge is efficiency and thermal considerations. More advanced processing and RF requires power and creates heat, and building wireless equipment into a compact pleasing form-factor makes thermal management more difficult. The smaller size and lower cost require the IC and packaging technologies to move to a higher level of integration, leading to increased integration complexity.
In this talk, the design challenges for the integration of High-Power Wi-Fi 5/6 Front End Module using advanced package approaches like Fan-Out Wafer-Level Packaging is presented. As an example, PA/Package co-design methodology is described on a High Power SOI-CMOS PA module for 2.4GHz WiFi 6 applications.


Underline digital video library

Criteria for Permanent-Magnet Materials

Reversible anisotropy manipulation via gate voltages in ferromagnet/oxide multilayers

Current driven domain wall dynamics across the angular momentum compensation point in epitaxially grown ferrimagnetic Ni-doped Mn4N thin films

Online Junction-Temperature Extraction Method for SiC MOSFETs Utilizing Turn-on Delay

Energy transfer dynamics in luminescent Eu(III) complexes with phosphine oxide ligands

High-Efficiency Power Amplifiers in RF-SOI technology: Challenges, Progress and Perspectives

Overview of RF Power Generation Using CMOS Technologies

D-band on GF 45RFSOI

Advanced 200 mm and 300 mm RF SOI Technologies Targeting 5G and beyond (6G) RF Front End Module SOC

Next generation of FD SOI platform to fulfill the requirements of millimeter-wave wireless systems

Next gen 5G RF Front End challenges

Addressing design challenges in High-Power Wi-Fi 5/6 Front End Modules

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