This report evaluates total ionizing dose degradation characteristics of ZnO and IGZO TFTs after x-ray irradiation. To fully understand the effect of the radiation on the two types of TFTs, we evaluated the structural, morphological, and binding states of the metal-oxide-semiconductor layers before and after X-ray irradiation.

Reliability Assessment of a-IGZO and ZnO Thin Film Transistors (TFTs) to X-ray irradiation

We propose a method to predict V-ramp V BD  using deep learning from OCD -spectrum. Through this, it was confirmed that inter-metal VBD degradation occurring in the LM layers of the COP structure V-NAND can be predicted. Modeling to predict VBD from OCD-Spectrum was performed using deep learning, and a highly accurate prediction model with R2 0.86 was obtained. Using this, V-ramp VBD can be predicted immediately at the process stage without waiting for fab-out.

V-ramp VBD Prediction Method Using OCD-spectrum and Deep-learning, and Application to Early Detection of V-NAND Low Metal Reliability Risk

This interdisciplinary study explores LED device stability in extreme saline environments. Using machine vision and AI recognition, it monitors LED degradation, providing early warnings for maintenance. The research identifies material changes and offers solutions applicable in consumer electronics and maritime industrial settings.

Machine Vision Observation, Artificial Intelligence Pattern Recognition, Protective Circuit Design, Material Characterizations, and Nanostructural Analysis for Investigating InGaN Green Light Emitting Diode Degradation in a Saline Environment

We evaluate the soft error rate (SER) in 18 nm FDSOI-planar SRAM and investigate the scaling trend of SER in FDSOI-planar. Our findings demonstrate that the SER in 18 nm FDSOI-planar is significantly lower than that of 28 nm FDSOI-planar. The total SER (aSER + nSER) in SRAM of 18 nm FDSOI-planar is lower than all the bulk-planar and bulk-FinFET technologies. We also examine the temperature dependence of SER in FDSOI-planar.

Comprehensive Study of SER in FDSOI-Planar: 28 nm to 18 nm Scaling Effect and Temperature Dependence

Determination of void nucleation from electromigration-induced critical stresses is a complex endeavor. In this study, we propose a combination of single link electromigration testing, augmented by large scale statistical evaluations, and physics-based simulations to extract the critical stresses. The calibration efforts lead to well-matched values of physical parameters such as effective diffusivity Deff, charge number Z*, and effective modulus B, and improve reliability assessments of early nucleation mechanisms down to the 4-sigma level.

A Novel Method for the Determination of Electromigration-Induced Void Nucleation Stresses

Total ionizing dose (TID) irradiation induced charge trapping and reliability are investigated in 3D sequential integrated (3DSI) devices and ICs. Strong, bias-dependent layer-to-layer coupling of TID response is observed. Ring oscillator (RO) response is consistent with the respective transistor responses in the upper and lower layers of the device structures. Circuit simulations reinforce the relative importance of transconductance degradation in pull-up <em>p</em>MOSFETs to the TID response of these ROs.

Charge Trapping in Irradiated 3D Devices and ICs

For the first time, we characterize the advanced Black Diamond(R) low-k dielectric and develop a physical model of time dependent dielectric breakdown (TDDB). We use the developed model to explain underlying physical mechanisms responsible for the lifetime degradation from the various integration steps.

Characterization and multiscale modeling of TDDB in state-of-the-art BEOL

In the semiconductor industry, enhancing the hardness of SiO x is an important issue. Previous studies have focused on the oxygen content dependence of hardness only in a limited region close to x = 2, where the hardness generally increases with increasing x. However, our exploration of SiO x revealed a different path to increase hardness: within the subregion 0 &lt; x &lt; 1.2, reducing the oxygen content led to an increase in SiO x hardness.

The Enhancement Mechanisms of SiOx Hardness via Manipulation of Oxygen Content

This work presents electromigration (EM) silicon data from realistic power grid device-under-tests (DUT). Power grids featuring logic gate equivalent quasi-load cells were generated by an automatic place-and-route tool to compare the EM failure location and lifetime behaviors. IR drop shifts and voiding location trends inside the grids were measured.

Electromigration Test Chip Experiments From Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis

SRAM SER measurements show a decrease in per-bit susceptibility at the 3-nm FinFET process compared to 5-nm, contrary to the 7-nm to 5-nm trend. Robust data across various supply voltages demonstrates pronounced exponential bias influence on 3-nm FinFET SRAM SER, distinguishing it from earlier processes. Simulation and modeling attribute these trends to Q crit and Q coll variations.

Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET

Non-destructive failure analysis is often limited to optical methods, which cannot provide the resolution necessary for analyzing state-of-the-art integrated circuits. Here, we present a powerful method based on scanning a single Nitrogen Vacancy center over the sample. This results in quantitative current density maps with high sensitivity and sub-50 nm resolution, detecting for example, open and short circuits. We demonstrate the technology by mapping current flow in a maze of 30 nm wide wires.

Scanning NV Microscopy – Tracing Currents at the Nanometer Scale

This paper investigates the alpha- and neutron-induced soft error rate (SER) in SRAMs manufactured with 3 nm bulk gate-all-around (bulk-GAA) process technology. The SER in SRAM of bulk-GAA is maximally 1.56X higher than in the same cell-size SRAM of bulk-FinFET. Moreover, shrinking cell size decreases the SER by a maximum of 0.38X in bulk-GAA. The SER of the minimum-size SRAM in bulk-GAA is lower than in bulk-FinFET.

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Reliability Assessment of a-IGZO and ZnO Thin Film Transistors (TFTs) to X-ray irradiation

V-ramp VBD Prediction Method Using OCD-spectrum and Deep-learning, and Application to Early Detection of V-NAND Low Metal Reliability Risk

Machine Vision Observation, Artificial Intelligence Pattern Recognition, Protective Circuit Design, Material Characterizations, and Nanostructural Analysis for Investigating InGaN Green Light Emitting Diode Degradation in a Saline Environment

Comprehensive Study of SER in FDSOI-Planar: 28 nm to 18 nm Scaling Effect and Temperature Dependence

A Novel Method for the Determination of Electromigration-Induced Void Nucleation Stresses

Charge Trapping in Irradiated 3D Devices and ICs

Characterization and multiscale modeling of TDDB in state-of-the-art BEOL

The Enhancement Mechanisms of SiOx Hardness via Manipulation of Oxygen Content

Electromigration Test Chip Experiments From Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis

Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET

Scanning NV Microscopy – Tracing Currents at the Nanometer Scale

Soft-Error Sensitivity in SRAM Manufactured by 3 nm Bulk Gate-All-Around (GAA) Technology

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