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In this work, H3TRB testing is conducted to compare the accelerated failure of vertical SiC power MOSFETs provided by two-well known manufacturers. A pronounced drain-to-source leakage is observed in tested devices from only one of the manufacturers, which is associated with a surface charge accumulation near the edge-termination structure of the device. Failure analysis of the device and package encapsulant is conducted to investigate the failure/degradation mode and to better understand the reliability physics. 

IRPS 2024 Main Conference

Surface Charge Migration in SiC Power MOSFETs Induced by High-Voltage H3TRB Testing

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#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Recent studies from Google and Facebook independently reported that in their large-scale server facilities, certain instructions were executed by specific CPU cores incorrectly. In a large server fleet, these errors often go undetected and hence are termed "silent". In this work, we investigate how individual defects within a device, when combined with background aging, can manifest as a critical fault in a logic path and potentially lead to corrupt execution errors in a multi-core system. 

Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers

Temporal characteristics of O2-doped MoS2 (MoS2:O)-based Ru/MoS2:O/Pt RRAM demonstrate that, basal-plane oxidation of MoS2 during its sputter-deposition in optimized O2 protects RRAM from environment. Mo3d (XPS) from 3-months’ MoS2:O revealed lesser Mo+6 (edge; MoO3)-to-Mo+4 (basal; Mo-O) ratio in MoS2:O than its un-doped counterpart, showing significant edge-oxidation (MoO3) in latter that adversely impacted monthly retention of RRAM having un-doped MoS2 film.

Impact of Edge and Basal Plane Oxidation on the Stability of Oxygen Doped MoS2-RRAM

This work proposes a methodology to predict thermal profiles in gate-all-around nanosheet circuits, considering thermal coupling in devices and interconnects. It establishes a cross-layer thermal resistance network model, validated against finite element simulation. This model predicts thermal effects on circuit performance and reliability. Neglecting these thermal couplings introduces significant errors. This work aids thermal-aware circuit design beyond the 3nm node.

A Thermal Profile Prediction Methodology for Nanosheet Circuits Featuring Cross-Layer Thermal Coupling Effect

This paper characterizes the accuracy degradation of an 8T-SRAM-based Analog Computing-In-Memory circuit due to aging effects. The measurement results from a 28nm CMOS test chip show that aging effects on 2T path and current mirrors increase computation errors and reduce power efficiency.

Measurement of Aging Effect of an Analog Computing-In-Memory Macro in 28nm CMOS

We investigate a drain current degradation in Fe-FET. This phenomenon is due to trapping/de-trapping charge rather than charged remnant polarization of ferroelectric layer. That is explained as a de-trapped compensation charge from the channel-side interfacial layer, and a trapped charge from substrate silicon channel. This modeling is confirmed by experimental and simulation results. Based on the thorough investigation, we propose pulse conditions for proper read operation and recommend physical parameters of channel IL in Fe-FET.

Drain Current Degradation Induced by Charge Trapping/De-trapping in Fe-FET

Ferroelectric field effect transistor can be read-out in a capacitive manner for improved energy efficiency, namely nvCAP mode. The reliability aspects such as endurance, retention and multi-level cell of nvCAP are evaluated. Impact of defect generation and charge-trapping on the endurance and retention behavior of nvCAP is investigated. The device sustains up to 107 program-erase cycles until the Con/Coff ratio becomes ~1. A C-V sweep performed on the fatigued device ‘recover’ the performance.

Reliability Assessment of Ferroelectric nvCAP for Small-signal Capacitive Read-out

Reliability of the clock signal is critical for the system in the nanometer technology. Duty cycle is one of the key metrics in the performance of clock signals. We explore the impact of wear out induced duty cycle shift in the local clock networks and propose adaptive clock gating for improving the reliability with the FinFET CMOS technology. The work demonstrates the duty cycle improvement during the lifetime with Intel FinFET technology.

Si Characterization of Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Local Clock Network

Phase change memory (PCM) is one of the most promising technologies for embedded nonvolatile memory because of high scalability and high-temperature data retention with Ge-rich GeSbTe. Ge-rich GST is affected by drift on both set and reset states which limits the stability of a multilevel cell and the accuracy of in-memory computing. This work presents a new methodology for precise, drift-stable MLC programming based on the weak reset operation to initialize the PCM device.

Drift compensation in multilevel PCM for in-memory computing accelerators

The geographical dispersion of manufacturing units makes real-time data aggregation a challenging task, especially as the scale of operations continues to expand. Moreover, manufacturers deal with sensitive and proprietary data and are reluctant to share data directly in areas such as lithography hotspot detection (LHD) due to concerns about IP protection. In this regard, In this work, we propose a QFL framework for LHD and offer a unique solution to address the aforementioned challenges effectively.

Robustness of Quantum Federated Learning (QFL) against “Label Flipping Attacks” for Lithography Hotspot Detection in Semiconductor Manufacturing

Silent Data Errors (SDE) are a unique category of errors that result in unpredictable system behavior that is often difficult to detect. SDEs can represent a serious concern to at-scale compute in data center operation. [1,2] This paper reviews data collected on SDE impacts to Artificial Intelligence (AI) workloads and Intel’s SDE mitigation tools available for use in the data center.

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Surface Charge Migration in SiC Power MOSFETs Induced by High-Voltage H3TRB Testing

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Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers

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