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In this paper, the impact of hot-carrier injection due to repetitive pulse switching of lateral DMOS transistors is studied. The proposed testing technique is used to emulate the dynamic switching conditions and the transistor reliability characteristics are compared with traditional DC measurement at constant gate/drain voltages. Experimental data shows that the repetitive pulse degradation under 6.6V drain stress is between two DC conditions (5.5V and 6.6V).

IRPS 2024 Main Conference

Repetitive Pulse Testing for LDMOS Transistor Reliability

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#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

The impact of scaling on the effects of mixed-mode electrical stress and ionizing radiation is assessed for third- and fourth-generation SiGe HBTs. When the devices were operating in forward-active mode, the fourth-generation technology showed a better radiation tolerance but worse hot carrier degradation due to mixed-mode stress. However, when the devices were operating in inverse-active mode, the trend was the opposite and the fourth-generation technology showed worse radiation tolerance but less mixed-mode degradation.

The Impact of Scaling on the Effects of Mixed-Mode Electrical Stress and Ionizing Radiation for 130-nm and 90-nm SiGe HBTs

We present a methodology to assess the damage on MOSFETs after non-conducting off-state induced hard breakdown. It's based on analyzing experimental S-parameters under common-source and common-drain configurations, which allows to identify the location of the damage by inspecting asymmetry in the electrical response. Furthermore, the technique is compatible with radiofrequency two-port test fixtures exhibiting one of the terminals grounded, such as those used for characterizing microwave devices. Using the technique, two breakdown mechanisms are observed.

Assessing Non-Conducting Off-State Induced Hard Breakdown for PD-SOI MOSFETs using an RF Measurement Technique

This paper introduces a novel three-dimensional approach to model threshold voltage variation (ΔVth) during TDDB stress of SiC trench MOSFETs in a wide temperature range T=273…523 K and studies the processes of ΔVth recovery at room temperature.

Threshold Voltage Drift and Recovery of SiC Trench MOSFETs during TDDB Stress

This study investigates hole-induced threshold voltage instability at high positive and negative gate stress in 4H-SiC power MOSFETs. Our study addresses the phenomenon of VT decrease by hole trapping that occurs during positive or negative high voltage gate screening, and the subsequent restoration of VT by applying a counterbalancing phenomenon such as electron-hole recombination or hole de-trapping to increase VT at positive gate bias. Therefore, threshold stability should be considered when applying gate screens.

Hole-induced threshold voltage instability under high positive and negative gate stress in SiC MOSFETs

P. Moens, et al. have proposed that CVS-TDDB cannot capture the impact of both electron and hole trapping mechanisms on the failure distribution function, in contrast to CCS-QBD. In this work, the investigation of electron trapping under the CCS is conducted in commercial Silicon dioxides thermally grown on 4H-SiC based on the electron trapping model proposed by M. Liang, et al. The model results are consistent with the measured results when the electron trapping dominants.

Investigation of the Electron Trapping in Commercial Thick Silicon Dioxides Thermally Grown on 4H-SiC Under the Constant Current Stress

The non-ideality in the subthreshold slope can be used to extract interface trap densities Ditvalues. We have applied this method to monitor changes in Dit under BTI stress and compare them to fixed oxide charges with regards to their impact on threshold voltage.

Measurement of the Dit changes under BTI-stress in 4H-SiC FETs using the subthreshold slope method

As compute node density increases exponentially in data centers, silicon faults undetected by the machine check architecture must be tightly managed. While many undetected faults will result in an application crash or a detected uncorrected error, those that manifest as silent data errors (SDE) are of greater concern because they may cause data loss or data corruption. We report the first detailed defect characterization regarding the types of defects that lead to SDE events.

Defect Mechanisms Responsible for Silent Data Errors

In this paper,we have developed a new convolution-based methodology to estimate the dynamic time-evolutionary degradation of pixel circuits in display applications. For the first time, we have enabled real-time observation of the threshold voltage changes over time in key driving TFTs under different bias conditions in transient simulations of pixel circuits. Additionally, we introduce an optimized 9T2C pixel compensation circuit,which is an approximately 50% improvement over the 0.73μA observed in the 7T1C configuration.

Convolution-Based Vth Shift Prediction and the New 9T2C Pixel Circuit in LTPS TFT AMOLED

Sentaurus TCAD is enabled to simulate parametric shift due to BTI and HCD in p-andn- GAASNSFETs.The framework is calibrated using ultra-fast measured BTI data at different VG andT, and HCD data at different VG and VD during and after stress.The isolated BTI and intrinsic HCD contributions are used in a cycle-by-cycle circuit simulation framework to determine Ring Oscillator(RO) degradation at various VDD, Tand Dynamic Voltage and Frequency Scaling(DVFS) conditions.The End-of-Life(EOL) device and RO degradation are compared.

A TCAD to SPICE Framework for Isolation of BTI and HCD in GAA-SNS FETs and to Estimate Impact on RO Under Normal and Overclocking Conditions

We reveal that negative body bias stress significantly enhances carrier energy near the bottom of the Fin, consequently exacerbating HCD in nFinFET. Furthermore, with the increase in negative body bias stress, the proportion of traps at the bottom of the Fin gradually increases, consequently weakening the body bias modulation effect. We introduce a novel characterization technique that employs body bias modulation of Vth to differentiate the distribution of traps within the vertical Fin direction.

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Repetitive Pulse Testing for LDMOS Transistor Reliability

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The Impact of Scaling on the Effects of Mixed-Mode Electrical Stress and Ionizing Radiation for 130-nm and 90-nm SiGe HBTs

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